which language is better between SystemC and System Verilog?

[lever]

I want to design the simulation platform for one asynchronous system. Because the system is complex, verilog or VHDL can not express clear and has no enough run speed.
But I find the system C is not good for asynchronous circuit. How can I simulate asynchronous system by systemC very well?
And I am not familiar with System Verilog. Also I can not find good documents to study System Verilog.
Is System C or System Verilog better?

 

[dumeHCM]

Re: which language is better between SystemC and System Veri

System Verilog is better

 

[_TopGun_]

Re: which language is better between SystemC and System Veri

System Verilog is better

Any suggestions why?

 

[dumeHCM]

Re: which language is better between SystemC and System Veri

Base on the number of Books and Publications

 

[lever]

Are there any good reference books about the system verilog ?