How can I understand the delay in verilog lib file

[lever]

for example, the OAI112

`resetall
`timescale 10ps/1ps
`celldefine
module OAI112(O, A1, B1, C1, C2);
output O;
input A1, B1, C1, C2;

//Function Block
`protect
or g1(o1, C1, C2);
nand g2(O, A1, B1, o1);

//Specify Block
specify

// Module Path Delay
if (C1 == 0 && C2 == 1) (A1 *> O) = (2.89:4.45:7.55, 2.94:4.74:9.06);
if (C1 == 1 && C2 == 0) (A1 *> O) = (2.79:4.37:7.49, 2.27:3.70:7.09);
if (C1 == 1 && C2 == 1) (A1 *> O) = (2.78:4.35:7.47, 2.06:3.34:6.34);
if (C1 == 0 && C2 == 1) (B1 *> O) = (3.41:5.23:8.83, 3.23:5.22:10.10);
if (C1 == 1 && C2 == 0) (B1 *> O) = (3.31:5.15:8.76, 2.56:4.18:8.14);
if (C1 == 1 && C2 == 1) (B1 *> O) = (3.29:5.12:8.72, 2.26:3.67:7.05);
(C2 *> O) = (5.18:8.19:13.98, 3.69:5.95:11.49);
(C1 *> O) = (4.64:7.29:12.35, 3.11:5.04:9.72);
endspecify
`endprotect
endmodule
`endcelldefine

when C1==0 and C2==1, the delay from A1 to O is
(2.89:4.45:7.55, 2.94:4.74:9.06);
I guess they are 28.9ps,44.5ps,75.5ps.....
But what mean are these numbers?

And I check the doc of this lib. the delay is not equal these delays in verilog file.

the following is from the lib doc:
AC Characteristics ( Temp=25.0°C Core Voltage=1.2V Process=Nominal Delay Unit=ps)
C1 C2 Path 1.500 ff 3.306 ff 7.287 ff 16.06 ff 35.40 ff 78.03 ff
tplh tphl tplh tphl tplh tphl tplh tphl tplh tphl tplh tphl
0 1 A1-O 87.67 117.8 100.8 128.7 127.1 147.4 181.8 179.1 301.0 234.9 562.6 343.2

So the delay that I get from the modelsim by verilog lib file is too short. And I don't know why.

 

[sunjimmy]

Hi,

Here is a short document to explain the timing information of lib file.
You can refer it to find your answer.

Hope it helps

Added after 4 minutes:

The attached file to explain .lib file



Added after 32 seconds:

The attached file to explain .lib file

 

[lever]

Yes, I can understand lib file. But I don't know why the difference between the information of lib file and specify timing information in the verilog simulation lib file.
It's miraculous