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Nice suggestion by mrflibble.
A few more suggestions:
1. Restrict the use of all-uppercase names to constants and parameters. That will reduce ambiguity from the code and constants/parameters become readily identifiable.
So you could do:
module network_controller_wb_master(
input wire...
Not sure about the exact syntax for NCVerilog. In ModelSim the switch to be included at command line goes like this:
+incdir+directory_for_include_files
There should be a similar switch for NCVerilog, if not the same one.
You will have to use:
`include "my_include_file.v"
In every file you...
$monitor in verilog syntax
Hi madhavisai,
Is it just a coincidence that your reply matches word-to-word to my reply which I had given exactly a month before you? Please refer to the link below.
-Saurabh
Re: detection of edge
I agree with avimit.
The pulse signal which is the output of edge detection mechanism is typically used as an enable input to load a particular value in a register/capture a particular value at a port in case of microprocessors. I am sure there are other applications too...
monitor verilog
Hi ASIC_intl,
$monitor, once invoked, continuously monitors the values of the variables/signals specified in the parameter list and displays all the parameters in the list whenever the value of ANY one of the variables/signals changes.
Since this system task continuously...
Answer to the 4th Question:
In Verilog this can be done by using non-blocking assignments.
always @ (posedge clk or posedge rst)
begin
if (rst == 1'b1)
begin
q0 <= <q0 rst. value>;
q1 <= <q1 rst. value>;
end
else
begin
q0 <= q1;
q1 <= q0;
end
end
Hope this helps.
In case of asynchronous signals, I believe it is OK to count number of positive going edges of the input signal in order to count the number of ones (i.e. number of times the input goes high).
Any other thoughts?
Hi kelvin_sg,
Are you referring to reset recovery time?
Please have a look at section 5.1 of this paper.
http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf
Hope this helps.
Regards,
Saurabh
Re: Reset Query
Hi vlsi_freak,
For the problem of asynchronous assertion and synchronous deassertion, there is an excellent paper by Cliff Cummings. It describes precisely this problem and proposes a solution to it. It is located at...
Hi ASIC_intl,
Posedge and negedge detection is a common requirement in microprocessors. One application could be to detect edge/level triggered events on certain GPIO inputs. I was in a team which was responsible for designing the GPIO module of a processor and we had to implement an event...
I am not sure, but you could try putting back-slashes (\) instead of front-slashes (/) in your path.
Try D:\output\v_out\design.out instead of D:/output/v_out/design.out
Windows OS uses backslash in its address path whereas linux uses frontslash.
Maybe windows is not able to locate the path...
Hi,
I am running CoWare SPD (2006 version) on Ubuntu 7.04. However, when I try to run the simulation of even demo programs on the tool, I get a code-compilation error from the tool. Could you please help me in troubleshooting the error?
The sequence of steps that I follow is:
1. Start SPD ...
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