Reset for synchronization of separate clock domains

[vlsi_freak]

Hi,

I am having two separate clocks in my module (Clock domain1 : 100 Mhz) and Clock domain 2 is 270 Mhz.

Do i need separate resets in my IO for resetting logic in these separate clock domains or else i can use a single system resets.

What all are recommended methods for synchronization when control signals move from a faster clock domain to a slower clock domain?

Please help me

Regards,
freak

 

[gliss]

Reset Query

If you're using asynchronous reset I don't think you need to worry about different clock domains.

 

[ljxpjpjljx]

Re: Reset Query

you mean the cross domain clock problem?

 

[vlsi_freak]

Re: Reset Query

Yes.

Reset for separate Clock domains.

I am having asynchronous assertion and synchronous deassertion.

Regards
freak

 

[omara007]

Re: Reset Query

Yes.

Reset for separate Clock domains.

I am having asynchronous assertion and synchronous deassertion.

Regards
freak

if the resst is synchronousely desserted .. i.e. it has to be synchronous to the clock edge when desserted .. this means that you need to either synchronize the first clock edge in both clock domains .. or have 2 seperate resets, one for each domain .. I also believe that you can have one global reset and a derived one ..

 

[kulkarni_saurabh]

Re: Reset Query

Hi vlsi_freak,

For the problem of asynchronous assertion and synchronous deassertion, there is an excellent paper by Cliff Cummings. It describes precisely this problem and proposes a solution to it. It is located at:

http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf

You can refer to section 6 of this paper for the solution.

Hope this helps.

Regards,
Saurabh

 

[Nir Dahan]

Reset Query

The above paper is very useful.
Make sure to cascade synchronize both resets as described.
it depends on your system requirements which cascade stage should come first (clk A or B)

good luck,

ND.
https://asicdigitaldesign.wordpress.com