vlsi_freak
Full Member level 2
Hi,
I am having two separate clocks in my module (Clock domain1 : 100 Mhz) and Clock domain 2 is 270 Mhz.
Do i need separate resets in my IO for resetting logic in these separate clock domains or else i can use a single system resets.
What all are recommended methods for synchronization when control signals move from a faster clock domain to a slower clock domain?
Please help me
Regards,
freak
I am having two separate clocks in my module (Clock domain1 : 100 Mhz) and Clock domain 2 is 270 Mhz.
Do i need separate resets in my IO for resetting logic in these separate clock domains or else i can use a single system resets.
What all are recommended methods for synchronization when control signals move from a faster clock domain to a slower clock domain?
Please help me
Regards,
freak