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i don't know your circuit, but i know two ways to eliminate flicker noise, for Switched circuits you can use a technique called auto zeroing, and i guess this is not the case, so i suggest to learn about a technique called: Chopping, it transfer the flicker noise spectrum to high frequency, you...
I would like to share my solution found for my problem, so anybody can profit from this thread, we must not put ; after cross event declaration ,
hope anybody can profit from this problem solution in the future
thnx
hello guys, i am tryong to generate a counter which has a 10*clock period, by doing a simple verilog A code, on cadence ,spectre simulatior, but the issue is that the simulation takes sooo long time,( +20 minutes ), so is this normal? my code is :
// VerilogA for lte, counter, veriloga
`include...
Sorry, yesterday, i didn't catch your reply, but actually, i don't wanna say that the config file creation didn't completed correctly coz of a missing file in my cadence:D:D, i will try to connect my TA in this grad project these days, to modifie my cadence version or something, and i will...
mmm, i don't know actually, using these keywords was a option, i begin by using a simple verilog code at gate level using ( not (out,inp) , and same problem , so i used the transistor level , but nothing at all, i will check the verilog editor ( mine in called nedit) and check the verilog...
okok, the simulation analysis is :transient i also pick a screen shot of its window, and you can find what it says to me when i run it at the last three sentences in the CIW
yes, my verilog code after existing it says it was sucessfully compiled, so there no error in code, here a screen shot of my work, knowing that,m the schematic and the functional are not in the same library as i understood from you
after setting the simulation paramters as transit and sepcifie the out and inp nodes, i press netlist and run and that error appear in the CIW:
Netlister:there were errors , no netlist was produced
....unsuccefull
knowing that after i click save and check after the schematic, it says that no...
hello, i have a problem wit that simple verilog code on Xilinux
module kMOS(out,select,p0,p1);
input p0,p1,select;
output out;
initial
begin
p0=0;
p1=0;
end
always @(select or p0 or p1)
case(select)
1`b0:out=p0;
1`b1:out=p1;
endcase
endmodule
when i compile it to check for syntax error...
yes i wanna simulate in modelsim, right, but from Xilinux, i load the file and compile it from Xilinux, the Modelsim appear at the process window in Xilunx then double click on it, it open directly modelsim simulate the file then run the simulation if it is a testbench file (i.e no need to force...
thnx for your reply, but in Xilinux, after checking for syntax, i select the testbench file, then behavioral simulation, then in the processes window, appear the "modelsim" i must click on it then the modelsim open automatically and run, but that doesn't happen, i can't find simulate from add as...
okok, after i created my symbol, after the verilog , i opened a new schematic as you told me, then wired all the necessary components (Vdd ,Vdc,gnd and a cap and Vpulse) then i check and save , without errors, then i chose tools-->analog environment then i labled the wire and set them to be...
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