[SOLVED] Verilog A Counter on Cadence

[kimo4ever]

hello guys, i am tryong to generate a counter which has a 10*clock period, by doing a simple verilog A code, on cadence ,spectre simulatior, but the issue is that the simulation takes sooo long time,( +20 minutes ), so is this normal? my code is :
// VerilogA for lte, counter, veriloga

`include "constants.vams"
`include "disciplines.vams"
`timescale 1ns/100ps
module counter(clk,rst);
input clk; voltage clk;
output rst; voltage rst;
integer i;
parameter real vh=1.2;
parameter real vl=0;
parameter real vth=(vh+vl)/2;


analog begin
@(cross(V(clk) - vth,+1));
if(i==0) begin
V(rst)<+ vh;
end
else if (i==1) begin
V(rst)<+ vl;
end
else begin
V(rst)<+ vl;
end

i=i+1;
if(i==9) i=0;


end

endmodule
thnx

 

[kimo4ever]

I would like to share my solution found for my problem, so anybody can profit from this thread, we must not put ; after cross event declaration ,
hope anybody can profit from this problem solution in the future
thnx