kimo4ever
Member level 2
hello, i have a problem wit that simple verilog code on Xilinux
module kMOS(out,select,p0,p1);
input p0,p1,select;
output out;
initial
begin
p0=0;
p1=0;
end
always @(select or p0 or p1)
case(select)
1`b0
ut=p0;
1`b1ut=p1;
endcase
endmodule
when i compile it to check for syntax error, this error appear
ERROR:HDLCompilers:26 - "kMOS.v" line 31 Macro reference `b0 is not defined
any idea about that error solution?
thnx in advance
module kMOS(out,select,p0,p1);
input p0,p1,select;
output out;
initial
begin
p0=0;
p1=0;
end
always @(select or p0 or p1)
case(select)
1`b0
ut=p0;1`b1
ut=p1;endcase
endmodule
when i compile it to check for syntax error, this error appear
ERROR:HDLCompilers:26 - "kMOS.v" line 31 Macro reference `b0 is not defined
any idea about that error solution?
thnx in advance