Verilog (Xilinux) simulation via modelsim

[kimo4ever]

i have a question in verilog (Xilinux)
now, i have written a code with verilog ,
module LTE(out,a,b,c);
input a,b,c;
output out;
wire w1;
and #1 (w1,a,b);
or #2 (out,w1,c);
endmodule

module stimulus;
reg A,B,C;
wire OUT;
LTE G1 (OUT,A,B,C);
initial
begin
$monitor($time,"A=%b,B=%b,C=%b,OUT=%b",A,B,C,OUT);
A=1;B=0;C=0;
#1 B=1;C=1;
#2 A=0;
#1 B=0;
#1 C=0;
#3 $finish;
end
endmodule

and i do everything and the syntax was correct, now, how to simulate it?
with modelsim or another method?
because i tried the modlsim but doesn't work, should i edit some properties in modelsim before run it?( because it should run without forcing the values of the input )
thnx in advance

 

[moottii]

Hi,
u mean that you don't know how to simulate your code?
if yes
after compiling , click the "simulate" (beside compile) and then select your testbench.
then click "to wave" from "add" (from menu bar) and then click Run.
That's it.

 

[kimo4ever]

thnx for your reply, but in Xilinux, after checking for syntax, i select the testbench file, then behavioral simulation, then in the processes window, appear the "modelsim" i must click on it then the modelsim open automatically and run, but that doesn't happen, i can't find simulate from add as you told me here

 

[moottii]

I thought u wanna simulate in modelsim not in xilinx...

 

[kimo4ever]

yes i wanna simulate in modelsim, right, but from Xilinux, i load the file and compile it from Xilinux, the Modelsim appear at the process window in Xilunx then double click on it, it open directly modelsim simulate the file then run the simulation if it is a testbench file (i.e no need to force values to input coz they has been assigned within the code ), but the modelsim stop simulation at a specific line and don't simulate it