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Recent content by Jorge Jesse Cantu

  1. J

    Timing diagram question

    Hi guys I was looking at the following code and timing diagram trying to understand it. My question is: How does this person derive the dataout binary numbers in accordance to the code? For example, when datain is 1010, why is dataout equal to 0111? From the process block I do not see this...
  2. J

    8 bit Mod VHDL question

    Hello fellow engineers/enthusiasts! I wrote the following program for an 8-bit modula N-bit counter, where N was a specified constant. I had to alter it a little bit due to my friend helping me, but what he altered I am confused about. My question is, why does he assign my cout to din within...
  3. J

    Check My Work for the following state machine diagram, table, minimization?

    For the following State Diagram below, I constructed a transition and output table, as well as used D-Flip Flops and K-maps to find the minimized equations. Can someone please check my work? The only confusion on my part came from my encoding of the states, as well as only having one error...
  4. J

    Writing test bench for my VHDL code?

    For my following code for a priority encoder, how would I write a test bench for this? I've seen several different examples for encoders and mux's but they all seem to differ and do not explain much. I would like someone to walk me through the process and maybe show me a test bench for my...
  5. J

    VHDL errors in my code?

    Thanks I edited my code above. But I am still getting this error: ERROR:HDLCompiler:806 - "C:/Users/Owner/Documents/vhdl/encoder/priorityencoder.vhd" Line 46: Syntax error near "process".
  6. J

    VHDL errors in my code?

    Hi guys! I just coded a 4 to 2 priority encoder and am getting the following errors: How do I fix these? Here is my code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity priorityencoder is port(en_l: in std_logic; --Active low enable din: in std_logic_vector(3 downto 0); --Active...
  7. J

    Timing diagram from VHDL clock divider code

    Cool I get that now! One more question, why does SIGOUT delayed from Strobe in the timing diagram? In the second process it asserts that SIGOUT(or IntNet) goes high when Strobe goes high so shouldn't they be asserted at the same time?
  8. J

    Timing diagram from VHDL clock divider code

    Hi guys, I have the following code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity MIDTERM2 is port(CLK : in STD_LOGIC; ACLR_L : in STD_LOGIC; SIGOUT : out STD_LOGIC); end Midterm2; architecture prob1 of MIDTERM2 is signal Strobe, IntNet ...
  9. J

    8 bit ring counter in VHDL

    Would this work? library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use IEEE.std_logic_unsigned.all; entity eightRC is port( CLK : in std_logic; EN: in std_logic; RST : in std_logic; Q: out std_logic_vector(7 downto 0) ); end eightRC; architecture behavior of...
  10. J

    8 bit ring counter in VHDL

    Metastability. I think self correcting means that I wanted to make it with some sort of combinational logic to ensure that it never goes metastable. Here is a picture describing a 4 bit self correcting counter. I personally was just confused and how to code this within my code:
  11. J

    8 bit ring counter in VHDL

    I am trying to design an 8-bit self correcting ring counter whose states are 11111110, 11111101,.......,01111111. This includes reset and enable inputs, where the counter goes to the initial state when reset is asserted and counts only if enable input is asserted. Now I think my code is correct...
  12. J

    Max frequency of clock with a deskewing flip flop

    Thank you!! I didn't realize it was that simple.
  13. J

    Max frequency of clock with a deskewing flip flop

    Yes, but the problem states a deskewing flip flop. Doesn't that mean that the data received is phase matched to the received clock? Or is it as simple as you state?
  14. J

    Max frequency of clock with a deskewing flip flop

    I have a question in my text book that I do not quite understand. I was wondering if someone could please explain what the question means? Such as, what is a deskewed flip flop. How would one find the max frequency of the clock from the diagram? Below is the question (8.83) with the...
  15. J

    A Johnson counter in VHDL

    Update: I did something dumb and posted the wrong code first, here is the right code:
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