Max frequency of clock with a deskewing flip flop

[Jorge Jesse Cantu]

I have a question in my text book that I do not quite understand. I was wondering if someone could please explain what the question means? Such as, what is a deskewed flip flop. How would one find the max frequency of the clock from the diagram?

Below is the question (8.83) with the corresponding diagram at the bottom:

 

[shahulakthar]

Fmax = 1 / (tsetup + tpd)
Fmax = 1 / (4.5 + 10.5)ns
Fmax = 66.666Mhz

clock skew (TSkew) is the difference in the arrival time between two sequentially-adjacent registers.

In you case, it is specified as same time clock arrive at both FF.

 

[Jorge Jesse Cantu]

Fmax = 1 / (tsetup + tpd)
Fmax = 1 / (4.5 + 10.5)ns
Fmax = 50Mhz

clock skew (TSkew) is the difference in the arrival time between two sequentially-adjacent registers.

In you case, it is specified as same time clock arrive at both FF.

Yes, but the problem states a deskewing flip flop. Doesn't that mean that the data received is phase matched to the received clock? Or is it as simple as you state?

 

[shahulakthar]

clock at each data flip-flop is phase-matched to the received clock.

 

[Jorge Jesse Cantu]

Fmax = 1 / (tsetup + tpd)
Fmax = 1 / (4.5 + 10.5)ns
Fmax = 66.666Mhz

clock skew (TSkew) is the difference in the arrival time between two sequentially-adjacent registers.

In you case, it is specified as same time clock arrive at both FF.

Thank you!! I didn't realize it was that simple.