Timing diagram from VHDL clock divider code

[Jorge Jesse Cantu]

Hi guys, I have the following code:

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Code VHDL - [expand]
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library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
 
entity MIDTERM2 is 
 port(CLK : in STD_LOGIC; 
 ACLR_L : in STD_LOGIC; 
 SIGOUT : out STD_LOGIC); 
end Midterm2; 
 
architecture prob1 of MIDTERM2 is 
signal Strobe, IntNet : STD_LOGIC; 
signal Hardware : STD_LOGIC_VECTOR(1 downto 0); 
signal aclr : STD_LOGIC; 
 
begin 
 aclr <= not ACLR_L; 
 SIGOUT <= IntNet; 
 Strobe <= ‘1’ when Hardware = “10” else ‘0’; 
 
 process(CLK, aclr) begin 
 if(aclr = ‘1’) then 
 Hardware <= “00”; 
 elsif(CLK’event and CLK = ‘1’) then 
 if(Strobe = ‘1’) then 
 Hardware <= “00”; 
 else 
 Hardware <= Hardware + 1; 
 end if; 
 end if; 
 end process; 
 
 process(CLK, aclr) begin 
 if(aclr = ‘1’) then 
 IntNet <= ‘0’; 
 elsif(CLK’event and CLK = ‘1’) then 
 IntNet <= Strobe; 
 end if; 
 end process; 
end prob1;

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And here is the following timing diagram for the code:



I get how the Hardware goes back to zero when strobe is asserted. But how do I know when strobe is asserted from the code? Why does it get asserted when Hardware = "10"? and why does the Hardware only count to "10" instead of "11"? I am trying to practice making timing diagrams from VHDL code. Also I do not know why SIGOUT is asserted in the timing diagram from the code. Some explanation would help me greatly!

 

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It's right there in the code.

Strobe gets asserted when Hardware = "10"

Strobe <= ‘1’ when Hardware = “10” else ‘0’;

Then hardware gets reset to "00" from "10" because of the following:

if(Strobe = ‘1’) then 
Hardware <= “00”;

Regards

 

[Jorge Jesse Cantu]

It's right there in the code.

Strobe gets asserted when Hardware = "10"

Strobe <= ‘1’ when Hardware = “10” else ‘0’;

Then hardware gets reset to "00" from "10" because of the following:

if(Strobe = ‘1’) then 
Hardware <= “00”;

Regards

Cool I get that now! One more question, why does SIGOUT delayed from Strobe in the timing diagram? In the second process it asserts that SIGOUT(or IntNet) goes high when Strobe goes high so shouldn't they be asserted at the same time?

 

[ads-ee]

IntNet is the registered version of Strobe (i.e. a 1-clock delayed version of Strobe). Near the beginning of the architecture IntNet is assigned to SIGOUT.

- - - Updated - - -

Hmmm, just noticed the entity is called MIDTERM2 and the architecture is prob1.

I sure hope you aren't trying to cheat on your exam.