Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I am learnig how to use the clone tool in virtuoso layout xl and wanted to know If it is posable to move a synchronized clone after it has been placed. Every time I try and get it in to prper positon I recive the folowing error
INFO (LX-1102): Instance '|M2' abutted to instance '|M6'.
INFO...
Hi. I am trying to interface a differential limiting amp with a single ended out put driver and am finding in nearly impossible to maintain 50% duty cycle. The limiting amp output is very nice 0.25 to 1.2V with crossings at about 50%. What I need is a circuit to convert this to 0 to 1.2V...
Hi. I would like to know if any one has experience making their own coil indicators (layout and models) for RFIC designs and how to go about it. I am trying to use inductive peeking for a CML receiver output and the minimum size of the inductors that come in the design kit are 100umx100um...
It has been a few years sense my last VLSI class and I would like some advice on what to use as a transistor size starting point for a given schematic. I am trying to simulate the input equalizer given in "A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18-µm CMOS Technology" from...
Solve - With a lot of gotchas!
to solve this problem only mark force or use not both. If that does not work reenlist export and then generate the module layout.
Below is a list of gotcha shortcomings I have found with allegro pcb modules:
-gotcha #1 - when using modules in allegro you can not...
Hi.
I am trying to make a reuse cell in alegro pcb and am having a heckof a time.
here is what I have done:
I made the schematic for the module
export net list (forcing it to create the module when I sink them)
Made the module layout
mad the module form the layout.
instantiated the module...
Hi.
I was wandering what people do in industry when writing VHDL code for synthesis? I have always used ( n downto 0 ) for std_logic_vectors. However when coding for RTL one needs to use ( 0 to n) so that the buss ordering matches the default ordering in virtuoso in order to avoid having to...
Hi
I am trying to verify a digital block which I synthesized using encounter and imported in to virtuoso for integration with analog components.
My question is is their an easy way of generating digital plots of buses automatically using skill? Currently I can generate the plots of single...
Hi.
I have a design rule mod I have been using for years to calculate a certain transistor geometry and after moving to a new design kit and version of Assura I am getting:
ERROR Text can't attach to layer: substrate is not connected.
WARNING LVS Run detected.
Non-legacy mode has been disabled...
Hi
I ma trying to re simulate an extracted design and getting strange results. It is acting as if all the inputs and outputs of sub blocks are floating and their is no interconnection between sub blocks.
Background:
I have tried extract and simulate one level say an inverter and it works fine...
Thanks.
I found that to this afternoon but get erros about:
**ERROR: (ENCOAX-618): Custom via definition for via 'via1Array_3' can not be created in OA, because the technology database is readonly. Connectivity will be broken in the saved OA database for these missing vias.
when I save as...
I was wandering if you ever got this to work properly and if so did you half to role your own mapping file? I am trying to translate a design using the ARM library and the ibm 8rf process and having difficulty. When I use the map file from the cmrf8sf directory encounter crashes (can encounter...
Sorry for the confusion and vague ness.
What I have is eight command decoders which watch eight data steams and if a command decoder detects data for it the data is latched to a 16 byte register. Each command decoder operates asynchronous with respect to the others. Because each command...
Hi.
I am trying to design a “vote of eight” which is proving to be changing and wanted to know if any one may have some out their may have some insight on how bet to do this.
I have eight sets of 16 lines which i need to find which 16 bit values occurs most often in the eight sets of lines...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
