Perferd bit order to avoid cds_thru in RTL synthisies of VHDL

[jmoore180]

Hi.
I was wandering what people do in industry when writing VHDL code for synthesis? I have always used ( n downto 0 ) for std_logic_vectors. However when coding for RTL one needs to use ( 0 to n) so that the buss ordering matches the default ordering in virtuoso in order to avoid having to use cds_thru to reorder the buss ie <15:0> to <0:15>. The reasoning for avoiding cds_thru is it is incompatible with some simulators (ultra_sim) and you haft to replace it with a 0.001 ohm resistor.

So what is more common in industry (n downto 0) with cds_thru or ( 0 to n)?

 

[chandramouliece]

actually counting in VHDL is from (0to n) only ...not from (n to 0)...always practically we caluclate from low to high...