low power differential to CMOS and maintaining dutty cycle in 65nm CMOS

[jmoore180]

Hi. I am trying to interface a differential limiting amp with a single ended out put driver and am finding in nearly impossible to maintain 50% duty cycle. The limiting amp output is very nice 0.25 to 1.2V with crossings at about 50%. What I need is a circuit to convert this to 0 to 1.2V single ended. I have tried running it straight in to an inverter and this destroys the 50% crossings (duty cycle). I have also looked at cross coupled inverters which are two slow for this application ( 10Gbs).

This seems like it would be a fairly common thing to need to do so if some one has a suggestion pleas let me know.

note: the signal is actually a random data stream when I say duty cycle I mean the positive pulse width is distorted. Also the reason for converting to single ended is so that I can get the driving force of CMOS inverters to drive the output driver.

I am trying to do this is in 1.2V 65nm CMOS.

 

[dick_freebird]

You might try an auto-biased inverter capacitively coupled,
that can at least remove the threshold-crossing error term.
Then you have to balance the rest of the taper chain to
keep PWD at a minimum, and probably use a low taper
factor so edges stay sharp and don't contribute to more.