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Recent content by jfyan

  1. J

    the problem of well isolation

    Hi Erikl, yes, you are right, it is not used usually, but used by mistake (somethimes for ESD consideration.) it is very nice to have discussion with you guys on the board. Regards, Jeff
  2. J

    the problem of well isolation

    Hi Erikl, maybe I need to clarify the answer agian. :-D see the doc i posted, and i think the Fig 4.4 is right for the cap of Fig4.3 (poly/nwell cap). for the part when vpoly is low and vnwell is high, the capacitance for the poly/nwell cap depends on frequency on it. I did the sim for this...
  3. J

    the problem of well isolation

    Hi Erikl, I think the bifurcation between us is whether the poly-over-nwell-cap is close to cox or not when Vpoly is low while Vnwell is high. my answer is yes. but, it depends on the operation frequency on the cap. for very low frequency, at which holes can be geneated fast enough, the high...
  4. J

    the problem of well isolation

    thanks Erikl, yes, the hole i reffered is the free charge when Vpoly - Vnwell is <0 . to be honesty, we did simulation to the two situations, one is Vpoly-Vnwell >0, the other Vpoly-Vnwell <0, the result is close to your statement. but, we just doubt the nwell-cap not-accurate modeling...
  5. J

    the problem of well isolation

    Re: inversion MOSFET against enhancement MOSFET Hi Erikl, yes, the serial connection of two caps will reduce the overall capacitance for small |Vpoly|, but with more negative Vpoly, the overall cap is still close to cox,because any small disturbance on Vpoly results in the change of "hole"...
  6. J

    the problem of well isolation

    hi Erik, thanks for your reply. but, for poly over nwell cap,i think it is very close to MIS (metal-isolator-semiconduction) cap, and many references said that there is still a same capacitance (~cox) when Vpoly is enough lower than the voltage on nwell (low frequency). here "enough" means, the...
  7. J

    the problem of well isolation

    hi erikl, can i inverter the polarity for the MOSCAP: can i tie the nwell to vdd, while poly to a lower voltage, is the same capacitance got? Jeff
  8. J

    Why jitter specification is needed for a spreading spectrum clock?

    Re: Clock jitter hi this is because it is clock, and it must be behaviored like a clock. used to synchronize the system. jeff
  9. J

    Anyone konw this circuit in the attachment?

    hi, it looks like a broadband amplifier using capacitive degeneration. jeff
  10. J

    Low frequency VCO implementation in digital and analog

    Re: low frequency VCO hi i think you can use divider to increase the freq. resolution, and the freq step can be realized by adding or removing capacitors. good luck. jeff
  11. J

    what happens to jitter of a clock when you divide it by 2?

    Re: divider jitter question https://www.designers-guide.org/Forum/YaBB.pl?num=1182149578
  12. J

    What are the effects of dividing the VCO output by 2 on output jitter?

    hi all, What are the effects of dividing the VCO output by 2 on output jitter? jeff
  13. J

    noise at the transient bias point

    hi yes you can. pss and pnoise can help you to do this. jeff
  14. J

    how to calculate or simulate the jitter of LVDS's receiver ?

    Re: how to calculate or simulate the jitter of LVDS's receiv hi, i think, SpectreRF can help you to do it by using pss and pnoise. good luck. jeff
  15. J

    What is the relationship between ESD and latch up?

    hi yes, you are right. as i know, like SCR structure, it will actrually induce latch up. so when design such structure, you must be careful. in normal mode, the latch up caused by esd protection ckt will not happen, but when esd test or a large electro-static charge inject, the latch up is used...
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