the problem of well isolation

[jfyan]

Re: inversion MOSFET against enhancement MOSFET

for poly over nwell cap, i think it is very close to MIS (metal-isolator-semiconduction) cap, and many references said that there is still a same capacitance (~cox) when Vpoly is enough lower than the voltage on nwell (low frequency).
here "enough" means, the generated "hole" is much more than doping level.

Sure, you're right, Jeff: a MOSCAP has a larger cap/area ratio than a MIS (or even a MIM) cap: the isolation layer of a MOSCAP (the gate oxide) is considerably thinner than the field oxide (FOX) of a MIS and still thinner than the (possibly high k) isolation layer of a MIM cap.

Your former question, however, was:

can i invert the polarity for the MOSCAP: can i tie the nwell to vdd, while poly to a lower voltage, is the same capacitance got?

Here, my answer still is: no. If the poly is negative against the n-well (with a min. difference >≈ Vth), a p+ inversion layer will build up below the poly, creating a reversely polarized junction in the n-well in series with the gate oxide cap. Due to the rather low doping of the n-well, this reversely polarized junction produces a relatively wide depletion width, resulting in a low cap/area ratio of this junction cap. Being in series with the proper gate oxide cap, this low cap/area ratio junction cap reduces the overall cap/area ratio considerably (if not actually determines it).

Hence an inversion layer MOSCAP (n-well positive, poly negative) - due to the serial junction cap - will always show a smaller cap/area ratio than an enhancement (or: accumulation) MOSCAP (n-well negative, poly positive).

Hope I could explain this comprehensibly!?
erikl

Hi Erikl,
yes, the serial connection of two caps will reduce the overall capacitance for small |Vpoly|, but with more negative Vpoly, the overall cap is still close to cox,because any small disturbance on Vpoly results in the change of "hole" only. this is because the amount of "hole" is much larger than the fixed charge. this means, the cap from junction is shorted.

thanks,
Jeff

 

[erikl]

Re: inversion MOSFET against enhancement MOSFET

yes, the serial connection of two caps will reduce the overall capacitance for small |Vpoly|, but with more negative Vpoly, the overall cap is still close to cox, because any small disturbance on Vpoly results in the change of "hole" only. this is because the amount of "hole" is much larger than the fixed charge. this means, the cap from junction is shorted.

Hi Jeff,
what do you mean with "hole"? Is it identical with the p+ inversion layer, which is built up when the negative Vpoly voltage surmounts the strong-inversion surface potential + Vt ?
In this case you're right saying "any small disturbance on Vpoly results in the change of "hole"", the change being an increase of carrier concentration just below the gate oxide in the n-well at the interface between oxide and silicon, with negligible thickness change.

This p+ inversion layer, however, constitutes a reversely polarized junction to the n-well in series with the gate cap, generating a depletion layer in this n-well, which is considerably thicker than the gate oxide (but has an εr about 3 times larger than that of the gate oxide).

Let's try an example: For a 0.18µm CMOS process, the gate oxide thickness is ≈4nm,
whereas the depletion layer thickness for (Vpoly-Vwell)=-2V creates a depletion layer thickness of about 40nm (The strong-inversion surface potential PHI(s) "eats up" about -1V , hence a residual reverse voltage of -1V is left over for the depletion region, s. the cited text from David M. Binkley's book below). This results in a cap/area ratio which is about a factor of 3 lower than that of the gate oxide cap. Being in series with the this cap, it essentially determines the total cap/area ratio.

I do not understand what you mean with "the cap from junction is shorted". What should short-cut this junction? The p+ inversion layer (your "hole"?) isn't directly connected to the n-well, only via the cap of the reversely polarized junction cap.

If you have a different opinion, just tell me, or simulate such a cap!

Regards, erikl

***********************************************
Citation from David M. Binkley:
"Tradeoffs and Optimization in Analog CMOS Design" p. 235

"For a 0.18µm CMOS process having [a retrograde n-well doping of] NB = 7e-17/cm³, the depletion region thickness is tdep = 0.043µm. This assumes VSB = 0V , PHI(0) = 2*PHI(F) = 0.913V at T=300K, and an approximate strong-inversion surface potential of PHI(s) = PHI(0) ≈ 2*PHI(F) + 4UT ≈ 1 V."
***********************************************

 

[jfyan]

thanks Erikl,
yes, the hole i reffered is the free charge when Vpoly - Vnwell is <0 .
to be honesty, we did simulation to the two situations, one is Vpoly-Vnwell >0, the other Vpoly-Vnwell <0, the result is close to your statement.
but, we just doubt the nwell-cap not-accurate modeling.
although, nwell cap has larger cap density than MIS structure, they have same mechanism, I think. so, for negative enough Vpoly - Vnwell, the overall cap is still close to Cox.
thank you.
Jeff

 

[jfyan]

Hi Erikl,
I think the bifurcation between us is whether the poly-over-nwell-cap is close to cox or not when Vpoly is low while Vnwell is high.
my answer is yes. but, it depends on the operation frequency on the cap.
for very low frequency, at which holes can be geneated fast enough, the high capacitance due to inversion can be observed.
in genearal, the doping-dependent generation rates are on the order of ~ms and the corresponding frequency in the Hz range, it is not expected in most applications. does above make sense?
thanks for you help so much.

Jeff

 

[erikl]

Thank you, jfyan,
for your answer, and the book excerpt about MOSCAPs! I think it is much clearer now, pls. s. below:

thanks Erikl,
yes, the hole i reffered is the free charge when Vpoly - Vnwell is <0 .
to be honesty, we did simulation to the two situations, one is Vpoly-Vnwell >0, the other Vpoly-Vnwell <0, the result is close to your statement. but, we just doubt the nwell-cap not-accurate modeling.

I think this result is true for a 2-terminal inversion MOSCAP (I will call it so, because it does not have the grounded surrounding p+ ring, described on pp. 72..74, or 98..100 of your PDF, bottom drawing of Fig. 4.2 , inversion MOSCAP in p-substrate, in this case). This is the type of MOSCAP I always was referring to.

... although, nwell cap has larger cap density than MIS structure, they have same mechanism, I think. so, for negative enough Vpoly - Vnwell, the overall cap is still close to Cox.

And this, I think, is true for a 3-terminal or pFET type inversion MOSCAP described by Fig. 4.5 (PMOS capacitor) on p. 75 (resp. p. 101 of your PDF).

I think the bifurcation between us is whether the poly-over-nwell-cap is close to cox or not when Vpoly is low while Vnwell is high.
my answer is yes. but, it depends on the operation frequency on the cap.

The a.m. simulation with "the result is close to your statement": was it a DC or AC simulation? If AC, which frequency did you use for your this simulation? If it was DC, wouldn't your result contradict the "Low frequency" inversion part of the C-V characteristic of Fig. 4.4 ? But may be this fig. does not relate to a 2-terminal inversion MOSCAP (Fig. 4.3), but to the 3-terminal type (Fig. 4.5). In this case I concede that the inversion capacitance is essentially the same as the accumulation capacitance.

I think our bifurcation is solved by this? It was an interesting discussion, thank you very much, Jeff!

Regards, erikl

 

[jfyan]

Hi Erikl,
maybe I need to clarify the answer agian. :-D
see the doc i posted, and i think the Fig 4.4 is right for the cap of Fig4.3 (poly/nwell cap). for the part when vpoly is low and vnwell is high, the capacitance for the poly/nwell cap depends on frequency on it.
I did the sim for this type of cap under the condition vpoly-vnwell =-1.5v (0.18u process), and found when the frquency is 100Hz, the capacitance is reduced to 1/3 of Cox, but, when the frequency is 1Hz, the capacitance is almost close to Cox (for the positive bias case.)
(pay attention to the leakage current from nwell to gnd.)

any question, just let me know.
regards,
Jeff

 

[erikl]

accumulation mode instead of inversion mode!

I did the sim for this type of cap under the condition vpoly-vnwell =-1.5v (0.18u process), and found when the frquency is 100Hz, the capacitance is reduced to 1/3 of Cox, but, when the frequency is 1Hz, the capacitance is almost close to Cox (for the positive bias case.)
(pay attention to the leakage current from nwell to gnd.)

Hi Jeff,
ok, you win! ;-)
However, I never ever use a cap just for blocking DC (and if so anyway, one still needs to calculate the capacitance according to the frequency to be transferred or short-cut). Filtering a 100Hz ripple is quite a good application, and there you're already down to ≈33%, as you state above.

Wouldn't it then be much better to use the MOSCAP in accumulation mode (Vpoly + , n-well -) instead, and save 2/3 of the necessary area? I always use it in accumulation mode!

Cheers, erikl

 

[jfyan]

Hi Erikl,
yes, you are right, it is not used usually, but used by mistake (somethimes for ESD consideration.)
it is very nice to have discussion with you guys on the board.

Regards,
Jeff