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Recent content by jawadysf

  1. J

    Outer conductor current calculation of Coaxial cable in HFSS

    I want to calculate the current flowing in the outer conductor of the Coaxial cable in case of mismatching at the load of the cable in HFSS. I have simulated the simple coaxial cable model in HFSS...Can anyone guide me how to measure the current flowing in the outer conductor of the Coaxial...
  2. J

    How to remove the delay from the output of DPLL(Urgent)

    I am recovering the clock from the DPLL as manchester data as input to the DPLL.But when i implemented the DPLL on SPARTAN3 Board,output clock exhibits a delay from the input clock. Can anyone suggest that how to remove this delay? Its urgent Thanks
  3. J

    How to remove the Glitches from the Output(Urgent)

    I have designed a Manchester Encoder in verilog but i am getting the glitches in the output,can any one suggest me the solution of it. I am already storing the output in the register. Its urgent Thanx
  4. J

    wait command implementing on hardware... URGENT

    i've developed the following code using counter but didn'nt get the required result...( () please help. module sync(clk,enable,signal,count); input clk; input enable; output [5:0] signal; output [2:0] count; reg [5:0] signal; reg [2:0] count; // Increment count on...
  5. J

    wait command implementing on hardware... URGENT

    how to replace the wait command when implementing the code on hardware? e.g in the following code how to replace the # for hardware implementation module word_gen(clk,cmd,data,status); input clk; output cmd; output data; output status; reg cmd,data,status; //Generation...
  6. J

    Parallel to Serial convertor(Urgent)

    Thanks
  7. J

    Parallel to Serial convertor(Urgent)

    design parallel to serial I need a 3 bit parallel to serial converter in verilog, can anyone suggest the solution Thanks
  8. J

    50MHz to 1MHz clock divder(Urgent Help)

    1 mhz clock thanks for your reply.
  9. J

    50MHz to 1MHz clock divder(Urgent Help)

    clock 1 mhz Hello frendz. I want to generate a 1 MHz clock with 50% duty cycle. f from the 50MHz in Spartan 3 SxLC.Can anyone suggest the solution for it? Its urgent Thanx
  10. J

    Digital Phase Lock Loop Design

    Hello Frendz I want to extract the clock from the Manchester coded input data ,i have tried to implement the different techniques of ADPLL but i didn't get the exact result. Can anyway suggest the working model or any type of solution to this problem.?
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