50MHz to 1MHz clock divder(Urgent Help)

[jawadysf]

clock 1 mhz

Hello frendz.
I want to generate a 1 MHz clock with 50% duty cycle. f from the 50MHz in Spartan 3 SxLC.Can anyone suggest the solution for it?

Its urgent
Thanx

 

[ombadei]

clock division 50 mhz

Should work fine for nicely divided frequencies but note that i consider this clock to be free running and i really should have some form of reset. Just change the 'n' value to suit your needs.

Still relatively new to VHDL but i have been playing with it since last year. Have fun.

Here's the code:

entity clk_div is
    Port ( 
	 	clkin : in  STD_LOGIC;
           	clkout : out  STD_LOGIC);
end clk_div;

architecture Behavioral of clk_div is
	signal clk_tmp : std_logic := '0'; 
	signal cnt : integer := 0;
	constant n : integer := 2; -- clock division factor= 2n
				             -- So, in this case: 
				             -- clkout = clkin/2n

begin	
		process (clkin,clk_tmp) begin 
			if (clkin'event and clkin='1') then 
				if ( cnt = n-1 ) then 
					clk_tmp <= not clk_tmp; 
					cnt <= 0; 
				else
					cnt <= cnt + 1;
				end if;		
			end if;	
			clkout <= clk_tmp; 		
		end process;


end Behavioral;

 

[jawadysf]

1 mhz clock

thanks for your reply.