Digital Phase Lock Loop Design

[jawadysf]

Hello Frendz

I want to extract the clock from the Manchester coded input data ,i have tried to implement the different techniques of ADPLL but i didn't get the exact result.
Can anyway suggest the working model or any type of solution to this problem.?

 

[Aya2002]

i am not interest in simulink but i can say that you can go to the matlab groupnews website. I am sure you will find the solution. As well, may be my friend will help you, his username is communication_engineer. I will ask him now.

Regards

 

[FvM]

i didn't get the exact result

What are your results?
Do you have a suitable oversampling reference clock? Also, if you want the PLL clock to be in phase with the bit clock without a 180° ambiguousity, it must take part in the synchronizing mechanism, e.g. decode the preamble or sync characters used in your link. A state machine decoding the manchester signal gives both, clock and data.

 

[osheen03]

hey can u pls send me the digital phase lock loop design code,

 

[md wasi ullah]

hello friends
can anyone help in designing the digital phase lock loop using verilog hdl
as i could able to design the digital circuit and verilog code but could able to get the correct output
how the phase detector output is given to low pass filter.
the low pass filter i am using it as up/down counter
is there any other way alternative then up/down counter for low pass filter

 

[mrflibble]

Regarding low pass filters...

For a quick quick implementation, averaging the last N values also has low pass filter properties...

Or you could do a FIR filter if you have more design effort to expend on this.

 

[gautamvsharma]

As for the pll block design you have to design phase sensitive detector and averaged-LPF (i.e., INTEGRATOR with integration factor(samples) = 8 or 16 or 32) afterwards you have to design VCO for the same and integrating these 3 entities results PLL. check it for jitter performance too.