wait command implementing on hardware... URGENT

[jawadysf]

how to replace the wait command when implementing the code on hardware?

e.g in the following code how to replace the # for hardware implementation

module word_gen(clk,cmd,data,status);
input clk;
output cmd;
output data;
output status;
reg cmd,data,status;
//Generation of syns of words
initial
begin
cmd=1'b1; //Syns of Command word is on for 1.5uses
status=1'b1; //Syns of Status word is on for 1.5uses
data=1'b0; //Syns of data word is off for 1.5uses
#1.5 cmd=1'b0; status=1'b0; data=1'b1; //Syns of data word is on for 1.5uses
#1.5 $finish; //Syns of commandn and status word is of for 1.5uses
end

endmodule

 

[FINALFANTASYFAN]

Not all HDL statements are synthesizeable. Some are just dedicated for simulation or easier-coding. Wait for a certain period of time is one of them.

If you want to achieve a delay of time which is much longer than the system clock, you can use a counter to wait. If it is relatively equal or even smaller than system clock you should take care about propagation delay of physic signal through route and LUTs to put into the path you need delay some LUTs. But it is complicated.

In addition, unfortunatly, Place and Route phase may cause some changes because of some LUTs added for routing through due to no direct ways between logic blocks or between logic blocks and IO blocks. As you know it's not the fact that all LUTs you need for a logic function are put next to each other.

 

[jawadysf]

i've developed the following code using counter but didn'nt get the required result...( () please help.


module sync(clk,enable,signal,count);
input clk;
input enable;
output [5:0] signal;
output [2:0] count;
reg [5:0] signal;
reg [2:0] count;

// Increment count on clock
initial
count = 0;
always @(clk or enable or count)

begin
if (enable)
count = count+1;
begin


if (count <= 3'b001)
signal[0] = 1'b1;
else if (count <= 3'b010)
signal[1] = 1'b1;
else if (count <= 3'b011)
signal[2] = 1'b1;
else
signal[3] = 1'b0;
signal[4] = 1'b0;
signal[5] = 1'b0;
end
end

endmodule

 

[FINALFANTASYFAN]

Of course you didn't.

1stly, your counter is misdesigned. You should use posedge of CLK to trigger the counter to make it Flip-flop, not latches on just enable like what you did.

2ndary, try thinking when your signal is assigned back to 6'b00 ???[/i][/b]