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Recent content by hosseineslahi7

  1. H

    Post-layout Results are not correct

    Thanks for your response. How can I control STI and WPE switches? I have not done that before? 1703845004 Yes, It is a good idea. I had to run simulations with/without the floorplan parasitic effect and see what happens. It is not a logical method but I had to optimize the floorplan to find...
  2. H

    Post-layout Results are not correct

    Dear experts, I have designed a simple design working as a level-shifter and buffer at 1GHz in GF22nm technology. Then, my colleague and I designed two roughly similar layouts for my design, however, we see completely different post-layout results. We carefully connected the back-gates, DEEP...
  3. H

    High speed buffer for measurement

    Thanks for this recommendation. My knowledge in terms of transmission line is low, so, my answer may not be correct. However, I am looking for a design that should be fully integrated into my 22nm layout. We will think about the transmission line option if we do not find any other solution.
  4. H

    High speed buffer for measurement

    Between 6-8GHz
  5. H

    High speed buffer for measurement

    Dear experts, I am trying to design a buffer after an up-conversion Mixer that can drive 50 ohm load for measurement. This buffer is supposed to be used for Mixer output measurement. However, we know that there is a huge load capacitance imposed by off-chip probes and wiring. This unwanted...
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    Testbench for THD and IIP3 simulations

    Dear all, I plan to simulate THD and extract IIP3 of a single transistor by using PSS and PSS+PAC analysis in cadence. I have used the testbench attached below to run simulations. Two bias tees are added to the input and output of the transistor and I have added a resistor of 50 ohm to the gate...
  7. H

    Sampling rate, delay, and the speed of a DAC

    Hi Sutapanaki, Thank you for your support. Everything is clear now. Regards
  8. H

    Sampling rate, delay, and the speed of a DAC

    Hi Sutapanaki, Thank you for your answer. Based on what you said, I have to look at the output characteristic of my design and find the settling time of my design. Am I right? Is it the time required for DAC to jump from one level to the next level (one LSB difference between two consequent...
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    Sampling rate, delay, and the speed of a DAC

    Hi All, I have designed a 4 bit DAC for biasing a neuron. I have some questions regarding the performance of my DAC. The post-layout simulations show INL and DNL lower than 0.16LSB. First, do they depend on the sampling rate or speed of the DAC? Second, what is the definition of the sampling...
  10. H

    Test circuit for high speed DAC measurement

    Dear all, I have designed a DAC the switching speed of which is around 1-2 GHz. I know that adding several analog test point (ATP) circuits for measuring the analog signals in low frequencies is inevitable. I have added a simple ATP structure reported in the following paper, however, this...
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    Design of a test point for analog signal measurement

    Hi All, I have designed an analog circuit in sub-threshold the frequency of which is tunned from kHz to a few MHz range. For measurement purposes, I know that a buffer with a small output impedance is needed for each voltage node and this buffer should be added to the layout before fabrication...
  12. H

    Canceling out the parasitic diode in Layout

    Hi Dominik, Thank you for your reply. The problem was solved by using HVTNFETTW. Cheers 1616141506 Thank you again, I followed your solution but I changed a bit the structure of extra circuit in my schematic. The problem is solved now. In addition, Dominik suggested a more straightforward...
  13. H

    Canceling out the parasitic diode in Layout

    Dear Dick, Thank you for your answer. However, the voltage over DNWEL should be greater than the Vdd of the circuit. For this reason, I should have access to this layer and connect it to an external voltage. In this case, a new pin is needed in both the layout and schematic because of LVS...
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    Canceling out the parasitic diode in Layout

    Dear All, I have designed a circuit in 22nm FDSOI technology which can offer frequency modulation if a bias is applied on the back-gate of a NMOS (HVTNFET model). In this layout, consequently, I should use deep NWELL to separate global substrate and local substrate of that particular transistor...
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    Include file into a verilog-A code

    Hi, I am trying to call or include some files into a specific verilog-A code. Each file encompasses a set of instructions. I used 'include (filename.include) in my code but this code cannot be compiled in AWR simulator. Could you please tell me how a file (verilog-A code) cqn be included in...
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