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Recent content by girih192002

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    inheritance global supply and ground pin in std cell

    Hi, Standard cells from fab are having global vdd and gnd. I wan to convert it into local pin limited to same digital gate. Can Anybody let me know how to solve it ?
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    Differential SAR ADC

    Hi I am seeing strange problem while simulation sar adc. ADC digital code for signal is as follows. Signal Code 0.5V 0000 0000 0 1000 0000 -0.5V 1111 1111 I would like to invert it so that it start from max code to min code. any suggestions about this ? and one more question is why I am...
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    LVDS Receiver Output Buffer design

    Thanks Dick Freebird, I guess, I have package wrongly. I got this ringing because of package inductance not through SSN.
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    LVDS Receiver Output Buffer design

    Hi All, I need to design output buffer at output of LVDS receiver. But, When I design it with inverter based buffer to drive package parasitics of 2 nH inductance and 3pF package cap. Output is ringing. Can any one suggest me some other way to design CMOS Buffer for LVDS Rx
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    Bandgap Reference Question

    supply voltage is 3.3 v.
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    Bandgap Reference Question

    Hi, To reduce Offset voltage Which would be best topology for OTA in Bandgap reference. Will 3 Mirrot OTA be good rather than two stage Miller OTA . Please, let me know.
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    LVDS Transmitter design reference Boni's paper

    Hi, I am working on LVDS Transmitter design and following boni's paper. I didnt understand what would be Bandwidth and gain of CMFB amplifier in this paper and Loop gain and margin. He has used Compensation Cap = 9.5 pF and Nulling resistor = 1.5 Kohm. please let me know your suggestions.
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    [SOLVED] 5:1 Mux in Serialiser

    Serialiser means SerDes Application
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    [SOLVED] 5:1 Mux in Serialiser

    Hi, Can anybody tell me how to implement 5:1 Mux for Serialiser ? Please, post any referred paper for it. Thank You
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    [SOLVED] CMOS 5:1 Serializer - help needed

    Hi George, Did you get any idea to implement 5:1 Mux ? I am also stuck in it. Please, share with me any paper if you have. Thank You - - - Updated - - - Hi George, Did you get any idea to implement 5:1 Mux ? I am also stuck in it. Please, share with me any paper if you have. Thank You
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    High Speed Serializer Architecture

    Hi, I am just confusing with below attached picture. I have some doubt. This is SerDes architecture. 1. Here How 8b/10b and 16b/20b encoded signal is converted into 8:2 multiplexer ? actually ODD parallel inputs to EVEN parallel outputs 2. Why do we need to generated always ODD and EVEN...
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    How to simulate 1/f noise reduction of CDS in simulator

    Hi Crutschow, I do not have Spectre RF. i am using Spectre with IC 6. It has option to do Transient Noise Analysis. But, It can only do Sampling noise. Is not it ? Correct me If I sound incorrect. I would like to see how CDS will reduce 1/f noise . I have seen some of IEEE paper, there...
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    How to simulate 1/f noise reduction of CDS in simulator

    Hi, I have designed CDS circuit. As given in literature, CDS reduce Flicker noise and sampling noise / KT/C noise. I know that, we can calculate KT/c through Transient Noise simulation in spectre. But, Please, let me know how can we simulate 1/f noise reduction through CDS
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    Integrator design problem because of 0.5V dip at the start

    Re: Integrator Design Problem Hi FvM, I am sorry for incomplete information. I have rectified the bug. Actually, Vcm was 2.5 V and I have given Offset = 2 V. so, There is pull down of 2.5 V to 2 V to start Integration. Thank you FvM
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    Integrator design problem because of 0.5V dip at the start

    Re: Integrator Design Problem Here is Circuit.
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