LVDS Receiver Output Buffer design

[girih192002]

Hi All,

I need to design output buffer at output of LVDS receiver. But, When I design it with inverter based buffer to drive package parasitics of 2 nH inductance and 3pF package cap. Output is ringing.

Can any one suggest me some other way to design CMOS Buffer for LVDS Rx

 

[dick_freebird]

This is more likely the crudeness of your lumped element
bond wire model. Then again everything rings somewhat
if you look close enough, with good enough equipment.

You might decide to slew-rate limit the output stage
(gate resistors are cheap and easy, so is using a very
high taper factor but this is poorly controlled). But you
do not state whether this is supply ringing or output
node ringing, whether the "kick" is related to shoot-
through current and high ground or supply impedance
or simply the bondwire resonance, etc. - this is where
I'd suggest you start looking.

Of course if you limit the slew rate too much you will lose
high data rate operation. Your package parasitics say to
me that you are in an inappropriate package for that,
if it's indeed a concern.

A more sophisticated bondwire model could change the
picture markedly. As a minimum, add the series R. If
you add the mutual inductances and capacitances, you
may just become depressed and go into Marketing,
though. ;p In any case you should validate your model
RLC values before making that career move.

 

[girih192002]

Thanks Dick Freebird,

I guess, I have package wrongly. I got this ringing because of package inductance not through SSN.