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Recent content by faizalism

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    Datasheet: Output capacitance at Static(DC) vs Dynamic(AC) ? diff

    Hi, I am referring to 1 of the datasheet and found that they stated different output capacitance at Static and Dynamic characteristic. ie. Static, Co output capacitance , min = -, max =7pF Dynamic, all output load = 25pF Why there is different for that capacitance setting? Any specific...
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    STA prime time - timing report

    Birdy, version 2010.06 SP3 4 ... any info about it?
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    STA prime time - timing report

    Hi, I have running primetime for my project and I found that hold violations are not same for report_analysis_coverage versus report_constraint. For your reference, below are my commands > report_analysis_coverage Type of Check Total Met Violated Untested...
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    Mos Current mode logic

    when I see your testbench, your Vdd=1.2V...and you purposely put A/Abar input (=1.8V) higher than vdd?
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    Mos Current mode logic

    Can I see your testbench? How you connect vdd?
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    thin & thick gate oxide

    Always, process has thick gate and thin gate transistors to support high voltage/low voltage designs. In the ends, it depends on you.
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    why tri-state logic cannot be buffered

    So, when 1 driver accessed, the rest of the driver need to be high-z. If you have buffer in btwn driver and bus, can you make sure it is high-z?
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    why clock inverters are preferred over clock buffers in CTS?

    Re: why clock inverters are preferred over clock buffers in It depends on your design...for practicality better if we can make sure the duty cycle ~40-60% to accommodate positive and negative edge trigger.
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    why tri-state logic cannot be buffered

    There is situation when few drivers want to access a bus. So, when 1 driver accessed, the rest of the driver need to be high-z.
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    VCS 'var' compiling issue

    Hi, I have problem compile verilog files that contained 'var' . Log file shows : Error-[SE] Syntax error Following verilog source has syntax error : "tryitout.sv", 27: token is 'var' input var real n_out, p_out; ^ System verilog keyword 'var' is not expected to be used in...
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    Testbench for IO buffer drive current spec ?

    Hi Erikl, So from the result, what we need to observe to make sure the buffer can support X Amp current. Is it constant voltage at X Amp. Thanks,
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    Testbench for IO buffer drive current spec ?

    Any info for this thread?
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    Testbench for IO buffer drive current spec ?

    Hi, I want to simulate for my IO current spec as in figure above, but I dont know how to setup the testbench. Eg. Let say I want to know whether my IO buffer can support for 6mA, how to simulate it? Thanks,
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    Problem with phase comparator output in a PLL circuit

    Re: PLL circuit problem It is output of phase detector, i think. Btw, what do you meant by "I did not use any fitler"
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    How to auto routing at schematic level (virtuoso schematic)

    Re: How to auto routing at schematic level (virtuoso schemat You are right rfsystem. But I need to submit the schematic to layout team, where most of the layout are juniors. :(
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