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Hello
I am running a power tool on my RTL code which is written in VHDL. I used many multidimetional array in my RTL. when i am trying to create vcd files in modelsim using wlf2vcd command it ignores these multidimetional array. what should i do to include these array. one more thing there are...
You are right and the reason for characterization is to provide top module's consstraint i.e. environment to lower sub module in order to synchronise the whole design. so first you syntheisis the lower submodule by giving them some constraint ans save it
2) read the sub module's netlist while...
when you syntheiss your rtl code using bottom up you need to characterize sub modele when you sythesis top module. first you synthesis lower module save it then when you synthesis top module characterize the sub module.
What i found is synthesis tool will take default library value for capacitance which result in no DRC violations even after synthesis or after P&R but if you choose other value you will get violation after sythesis as well as after P&R using STA in primetime. so is it really need to change...
I got same violation for max capicitance but what should i do to remove it is there any way i can resolve max_capacitance violation like setup and hold.
Re: compile_ultra multiple times
Tahnx for uploading this script file i use you constraint file as a reference and when i give
set_load [expr 2 * [load_of $REFLIB/$DFFCELL/$DFFCELL_IN_PIN]][all_output] command i got following error
Error: value '2.98966_sel44' for option 'value' not of...
I am new with ic compiler and i learning it i have few questions
1) i synthesis FIFO in dc compiler and remove all the violation now when i move to ic compiler and create milkyway library and when i open it i got following warnings.
Warning: DesignRule is defined with invalid metal-to-via...
thanx subhash,
what i do is i am synthesizing asynchronous FIFO in dc compile using topdown methodology. I gave constrained and check for the violation. In dc all the timings are met and no violatioin but when i check sta in Prime Time it gives me violation in internal logic there are two...
i have a questions related set_max_delay how much exactly it should be assigned means what should be the proper amount for set_max_delay because if i use it less than clock it doesn't have any effect on timing report i.e still have setup violation. other then that if i assigned more than clock...
I have synthesis asynchonous fifo in dc compiler now i am trying solved violation in PrimeTime. Most of violation is from reset to input posr of subdesig so i set false path to remove the violation now when i check report_timing i got negative slack due to my memory that i want to improve how...
I setup .synopsys_pt.setup and i am trying to use it fifo i synthesis my fifo using 90nm library i am using same library for prime time it link the library but give me following information
Information: 204 (91.07%) library cells are unused in library saed90nm_max.....
Information: 224...
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