hbeck
Junior Member level 2
Hi all,
I'm somehow confused. I synthesized my design (post-layout) with the Design Compiler and the setup timing was met. Without any knowledge of the subsequent clock tree insertion I assume the values for clock uncertainty, transition time and latency as listed below:
The timing report after synthesis gives following result:
In Primetime I read the *.ddc and *.sdc generated by DC and display the endpoint slack of my entire design and there are a lot of of setup violations :shock:
So should I re-synthesis my design with new timing constraints or is this a misunderstanding of the PrimeTime methodology?
Any help is appreciated!
Versions: DC F-2011.09-SP4 and PT F-2011.12-SP3 both running on CentOS 6.2
I'm somehow confused. I synthesized my design (post-layout) with the Design Compiler and the setup timing was met. Without any knowledge of the subsequent clock tree insertion I assume the values for clock uncertainty, transition time and latency as listed below:
Code:
set clk clk
set clock_period 3.33
set clock_uncertainty 0.3
set clock_transition 0.3
set clock_latency 1
create_clock -name clk -period $clock_period [get_ports $clk]
set_dont_touch_network [get_ports $clk]
set_fix_hold clk
set_clock_uncertainty -setup $clock_uncertainty clk
set_clock_uncertainty -hold $clock_uncertainty clk
set_clock_transition $clock_transition clk
set_clock_latency $clock_latency clk
set_ideal_network [get_ports $clk]The timing report after synthesis gives following result:
Code:
Timing Path Group 'clk'
-----------------------------------
Levels of Logic: 31.00
Critical Path Length: 2.92
Critical Path Slack: 0.00
Critical Path Clk Period: 3.33
Total Negative Slack: 0.00
No. of Violating Paths: 0.00
Worst Hold Violation: -0.24
Total Hold Violation: -8.22
No. of Hold Violations: 35.00
-----------------------------------In Primetime I read the *.ddc and *.sdc generated by DC and display the endpoint slack of my entire design and there are a lot of of setup violations :shock:
Code:
pt_shell> report_global_timing
Setup violations
---------------------------------------------------------
Total reg->reg in->reg reg->out in->out
---------------------------------------------------------
WNS -0.35 -0.35 0.00 0.00 0.00
TNS -26.44 -26.44 0.00 0.00 0.00
NUM 335 335 0 0 0
---------------------------------------------------------So should I re-synthesis my design with new timing constraints or is this a misunderstanding of the PrimeTime methodology?
Any help is appreciated!
Versions: DC F-2011.09-SP4 and PT F-2011.12-SP3 both running on CentOS 6.2
Last edited:
