er2212
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I am new with ic compiler and i learning it i have few questions
1) i synthesis FIFO in dc compiler and remove all the violation now when i move to ic compiler and create milkyway library and when i open it i got following warnings.
Warning: DesignRule is defined with invalid metal-to-via enclosure layers 'NWELL' and 'DIFF'. (line 1920). (TFCHK-082)
Warning: DesignRule attribute 'layer2' is assigned a non-physical layer 'DNW'. (line 1930) (TFCHK-079)
Warning: DesignRule is defined with invalid metal-to-via enclosure layers 'NWELL' and 'DNW'. (line 1933). (TFCHK-082)
Warning: DesignRule is defined with invalid metal-to-via enclosure layers 'PO' and 'DIFF'. (line 1940). (TFCHK-082)
Warning: DesignRule is defined with invalid metal-to-via enclosure layers 'DIFF' and 'CO'. (line 1948). (TFCHK-082)
Warning: DesignRule attribute 'layer2' is assigned a non-physical layer 'RPOLY'. (line 2134) (TFCHK-079)
Warning: DesignRule is defined with invalid metal-to-via enclosure layers 'PIMP' and 'DIFF'. (line 2142). (TFCHK-082)
Warning: DesignRule is defined with invalid metal-to-via enclosure layers 'NIMP' and 'DIFF'. (line 2148). (TFCHK-082)
Warning: DesignRule is defined with invalid metal-to-via enclosure layers 'DIFF_25' and 'DIFF'. (line 2154). (TFCHK-082)
Warning: DesignRule attribute 'layer1' is assigned a non-physical layer 'HVTIMP'. (line 2157) (TFCHK-079)
Warning: DesignRule is defined with invalid metal-to-via enclosure layers 'HVTIMP' and 'DIFF'. (line 2160). (TFCHK-082)
Warning: DesignRule attribute 'layer1' is assigned a non-physical layer 'LVTIMP'. (line 2163) (TFCHK-079)
Warning: DesignRule is defined with invalid metal-to-via enclosure layers 'LVTIMP' and 'DIFF'. (line 2166). (TFCHK-082)
Warning: DesignRule is defined with invalid metal-to-via enclosure layers 'SBLK' and 'DIFF'. (line 2173). (TFCHK-082)
Warning: DesignRule is defined with invalid metal-to-via enclosure layers 'SBLK' and 'PO'. (line 2180). (TFCHK-082)
Warning: DesignRule is defined with invalid metal-to-via enclosure layers 'PIMP' and 'PO'. (line 2192). (TFCHK-082)
Warning: DesignRule is defined with invalid metal-to-via enclosure layers 'NIMP' and 'PO'. (line 2198). (TFCHK-082)
Warning: Layer 'M1' has a pitch 0.32 that does not match the recommended wire-to-via pitch 0.33. (TFCHK-049)
Warning: Layer 'M2' has a pitch 0.32 that does not match the recommended wire-to-via pitch 0.36. (TFCHK-049)
Warning: Layer 'M3' has a pitch 0.64 that does not match the recommended wire-to-via pitch 0.36. (TFCHK-049)
Warning: Layer 'M4' has a pitch 0.64 that does not match the recommended wire-to-via pitch 0.36. (TFCHK-049)
Warning: Layer 'M5' has a pitch 1.28 that does not match the recommended wire-to-via pitch 0.36. (TFCHK-049)
Warning: Layer 'M6' has a pitch 1.28 that does not match the recommended wire-to-via pitch 0.36. (TFCHK-049)
Warning: Layer 'M7' has a pitch 2.56 that does not match the recommended wire-to-via pitch 0.36. (TFCHK-049)
Warning: Layer 'M8' has a pitch 3.84 that does not match the recommended wire-to-via pitch 0.465 or 0.5. (TFCHK-049)
Warning: Layer 'M9' has a pitch 5.12 that does not match the recommended wire-to-via pitch 0.935 or 0.9. (TFCHK-049)
what are exactly this warnings because during placement it fail in tlu_rc model can anyone help me
1) i synthesis FIFO in dc compiler and remove all the violation now when i move to ic compiler and create milkyway library and when i open it i got following warnings.
Warning: DesignRule is defined with invalid metal-to-via enclosure layers 'NWELL' and 'DIFF'. (line 1920). (TFCHK-082)
Warning: DesignRule attribute 'layer2' is assigned a non-physical layer 'DNW'. (line 1930) (TFCHK-079)
Warning: DesignRule is defined with invalid metal-to-via enclosure layers 'NWELL' and 'DNW'. (line 1933). (TFCHK-082)
Warning: DesignRule is defined with invalid metal-to-via enclosure layers 'PO' and 'DIFF'. (line 1940). (TFCHK-082)
Warning: DesignRule is defined with invalid metal-to-via enclosure layers 'DIFF' and 'CO'. (line 1948). (TFCHK-082)
Warning: DesignRule attribute 'layer2' is assigned a non-physical layer 'RPOLY'. (line 2134) (TFCHK-079)
Warning: DesignRule is defined with invalid metal-to-via enclosure layers 'PIMP' and 'DIFF'. (line 2142). (TFCHK-082)
Warning: DesignRule is defined with invalid metal-to-via enclosure layers 'NIMP' and 'DIFF'. (line 2148). (TFCHK-082)
Warning: DesignRule is defined with invalid metal-to-via enclosure layers 'DIFF_25' and 'DIFF'. (line 2154). (TFCHK-082)
Warning: DesignRule attribute 'layer1' is assigned a non-physical layer 'HVTIMP'. (line 2157) (TFCHK-079)
Warning: DesignRule is defined with invalid metal-to-via enclosure layers 'HVTIMP' and 'DIFF'. (line 2160). (TFCHK-082)
Warning: DesignRule attribute 'layer1' is assigned a non-physical layer 'LVTIMP'. (line 2163) (TFCHK-079)
Warning: DesignRule is defined with invalid metal-to-via enclosure layers 'LVTIMP' and 'DIFF'. (line 2166). (TFCHK-082)
Warning: DesignRule is defined with invalid metal-to-via enclosure layers 'SBLK' and 'DIFF'. (line 2173). (TFCHK-082)
Warning: DesignRule is defined with invalid metal-to-via enclosure layers 'SBLK' and 'PO'. (line 2180). (TFCHK-082)
Warning: DesignRule is defined with invalid metal-to-via enclosure layers 'PIMP' and 'PO'. (line 2192). (TFCHK-082)
Warning: DesignRule is defined with invalid metal-to-via enclosure layers 'NIMP' and 'PO'. (line 2198). (TFCHK-082)
Warning: Layer 'M1' has a pitch 0.32 that does not match the recommended wire-to-via pitch 0.33. (TFCHK-049)
Warning: Layer 'M2' has a pitch 0.32 that does not match the recommended wire-to-via pitch 0.36. (TFCHK-049)
Warning: Layer 'M3' has a pitch 0.64 that does not match the recommended wire-to-via pitch 0.36. (TFCHK-049)
Warning: Layer 'M4' has a pitch 0.64 that does not match the recommended wire-to-via pitch 0.36. (TFCHK-049)
Warning: Layer 'M5' has a pitch 1.28 that does not match the recommended wire-to-via pitch 0.36. (TFCHK-049)
Warning: Layer 'M6' has a pitch 1.28 that does not match the recommended wire-to-via pitch 0.36. (TFCHK-049)
Warning: Layer 'M7' has a pitch 2.56 that does not match the recommended wire-to-via pitch 0.36. (TFCHK-049)
Warning: Layer 'M8' has a pitch 3.84 that does not match the recommended wire-to-via pitch 0.465 or 0.5. (TFCHK-049)
Warning: Layer 'M9' has a pitch 5.12 that does not match the recommended wire-to-via pitch 0.935 or 0.9. (TFCHK-049)
what are exactly this warnings because during placement it fail in tlu_rc model can anyone help me
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