[STA] Capacitance Report

[ivlsi]

Hello All,

How can I report the capacitance violations? What command should I use?
When should I report the capacitance violations?
How does the report look like?

Thank you!

 

[yx.yang]

You can use "report_constrain -max_capacitance -verbose" in DC and PT.

 

[er2212]

I got same violation for max capicitance but what should i do to remove it is there any way i can resolve max_capacitance violation like setup and hold.

 

[dftrtl]

You need to buffer the path.

 

[ivlsi]

"report_constrain -max_capacitance -verbose" - does the command report constraints or violations?

- - - Updated - - -

You need to buffer the path.

Should the buffers be inserted by P&R tools?
Might the capacitance violations be fixed by up-sizing the driving cells (cells, which drive the violated net)?
Are the capacitance and fanout violations the same thing? Why does synthesizer not fix these violations automatically?
Do the capacitance violations usually appear after P&R?

Thank you!

 

[er2212]

What i found is synthesis tool will take default library value for capacitance which result in no DRC violations even after synthesis or after P&R but if you choose other value you will get violation after sythesis as well as after P&R using STA in primetime. so is it really need to change default valus for capacitance or is it best to use default value from library??????????

 

[dftrtl]

Synthesis generally uses wire model to report load voilations. You can change wire model accordingly reflecting your technology node.