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Recent content by Elektronman

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    From FPGA project to mass production: looking for advices

    Hi there, My FPGA-based portable HDMI video-recorder project is done and the prototype works ok (well sort of...). Next step now is going to mass production. A convertion from FPGA to ASIC is required and this could require some time. considering the possibility of mass-producting this...
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    Verilog code help for up_down counter with enable and reset

    Re: Verilog code help ,,,,؟‏ normally to create a delay, you use an internal counter that increases at every clock tick. Then after a threashold is reached, you reset this counter and fire the event (up_down counter) or you could check for a particular bit on the counter if you know what you...
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    WANTED: model type/datasheet for this unknown LCD?

    Are you sure? And waht about the datasheet?
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    WANTED: model type/datasheet for this unknown LCD?

    Hello this is a 128x64 LCD. It is ks0108 -compatible but I'm not able to find datasheet for this. Strangely enough, it has 22 pins (while most LCDs have 20 pins). The purpose of those extra 2 pins (21, 22) is unknown to me. I'm trying to interface it with PIC16f876a, without success. pin 19 and...
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    Does anyone know how this TL082 opamp-based circuit works?

    This is a dollar tester circuit, it is used to distinguish fake notes from the real ones. The magnetic ink present in US dollar is detected through a magnetic head (like those used in tapes audio recorders). and a LED lights up if the note is real Does anyone know how this work in practice...
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    Looking for ARM-based soft core processor for Xilinx Spartan 6

    Hello, do exist ARM softcore processors for Xilinx Spartan 6 FPGA? I know that for Altera FPGAs there is Cortex M1, I wonder if something similar exists for Xilinx. I looked around but was unable to find informations Thank you
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    Interfacing Spartan 6- Atlys board with DDR memory without EDK

    I "solved" the problem using a soft core processor, I have other problems now (unable to stream HDMI pictures at a decent speed because of busted USB port and my only alternatives are either the SLOW UART or Ethernet which I'm unable to operate :sad:.... I know life is painful... ) will put...
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    Is there any application that is dominated by FPGA?

    FPGAs are used a lot in the avionics and space industries. However in production industry, FPGA are used more for creating prototypes of the final product. FPGAs still suffer from being too expensive and power consuming, so they are not good for mass production. My 2 cents Elektronman
  9. E

    Interfacing Spartan 6- Atlys board with DDR memory without EDK

    I'm completely stuck in this problem. Every attempt I try to drive the DDR2 RAM module seems to fail.... I don't know where to hit my head now... :-? does anyone know of a working example with DDR2 ?
  10. E

    FSM in Verilog problem: why leds don't light up?

    looks like the PLL doesn't work... At this point I start suspecting that my Atlys board has a different DDR2 RAM memory chip... and of course the MIG-generated core fails
  11. E

    Interfacing Spartan 6- Atlys board with DDR memory without EDK

    Hello fpgaengineer, I stopped working on the simulation as I started struggling with the "real" hardware ( I'm still trying to find out what is really happening in the above-mentioned example, although I don't have much time now to dedicate to Atlys; and lately my dedication to the project has...
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    FSM in Verilog problem: why leds don't light up?

    BTW, I investigated a little the problem. Looks like c3_clk0 is fired only once, so state always remains at 0 (Very strange behaviour )
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    FSM in Verilog problem: why leds don't light up?

    I tried both the advices, but nothing changed... .... this is the log: WARNING:HDLCompiler:872 - "D:\Atlys_info\atlys_ddr_test-20110731\atlys_ddr_test\ipcore_dir\ddr2\user_design\rtl\mcb_controller\mcb_raw_wrapper.v" Line 681: Using initial value of allzero since it is never assigned...
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    FSM in Verilog problem: why leds don't light up?

    Hello, I'm working with a sample project for Digilent Atlys that can be found here: https://tristesse.org/pub/atlys_ddr_test-20110731.zip I have modified state 0 and state 1 of the FSM, so that it light some leds at certain spots. ( This is done mainly for debugging) I have been working on this...
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    Quick (and easy) question about Verilog / UCF editing

    Hello, what is the difference between writing: NET "leds[0]" LOC = "U18" | IOSTANDARD=LVCMOS25; NET "leds[1]" LOC = "M14" | IOSTANDARD=LVCMOS25; NET "leds[2]" LOC = "N14" | IOSTANDARD=LVCMOS25; NET "leds[3]" LOC = "L14" | IOSTANDARD=LVCMOS25; NET "leds[4]" LOC = "M13" |...

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