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Interfacing Spartan 6- Atlys board with DDR memory without EDK

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I will try upgrading ISE as soon as possible. Though.. I really do not understand how IDE version can affect the result..

Well, when the code monkeys at xilinx change some code (for example tcl script related to your favorite core) then anything is possible. :p

However for this particular core I doubt there is a problem due to ISE version. As in ... joelby has tested it on ISE 12.4. I tested it on both 13.3 and 14.2 ... all working. That said, it probably can't hurt to do a fresh new install of ISE 14.2 and then re-try things. Maybe you have a dodgy install somewhere, who knows.

*checks* Or maybe just get ISE 14.3, which I see is available...

Mmmmh.... Error We cannot fulfill your request due to technical difficulties. Please try again later.

I know that error. That error means "we just released a new version of ISE and our server in the basement cannot handle the stupendous bandwidth of those 3 simultaneous downloads". Guess I'll wait a few days.
 

I did the "upgrade" to 14.3 (actually I removed the old version and installed the new one)..... nothing changed :-(
I ran tb_ddr2_interface on ISIM, and after 18,500,000 ps, c3_calib_done is still 0 and DDR2DQ is till ZZZ...
 

I did the "upgrade" to 14.3 (actually I removed the old version and installed the new one)..... nothing changed :-(

Well, that's a good thing! At least things are consistent! :)

I ran tb_ddr2_interface on ISIM, and after 18,500,000 ps, c3_calib_done is still 0 and DDR2DQ is till ZZZ...

Wait, what?!?

I think I just worked out what the problem is. The problem is you are a silly reading impaired monkey. And to compound the problem I am also a silly reading impaired monkey. :-/

The part where you don't fully read other people's post is right here. First sentence. " ... c3_calib_done goes from 0 to 1 at 454.5738 us. "

The part where I don't fully read other people's post is the post right above it. "... I ran 1,000,000ps (aka 1ms) of simulation ". Yeah ... no. That would be 1,000,000ps (aka 1 microsecond). Not the 1 milisecond you were hoping for. ;) I didn't notice the 1,000,000 ps vs 1 ms mismatch earlier. Doh.

At any rate, run it for 1,000,000,000 ps (aka 1ms, no really) and life shall be peachy. Incidentally, you can just fill in "1ms" as value in the "Simulation Run Time" field. That's what I used. And as originally posted, stuff happens at 454.5738 us (aka 454,573,800 ps)

So hopefully that'll solve it. :)
 
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You are right.. damn 8-O.. the combination of software-noobness and winter is terrible..LOL
Anyway, I left ISim running until the 454,573,800ps mark: this is where c3_calib_done finally goes to 1 on my simulator; Infinite patience was the key LOL
As a related side note ISim took a shocking HUGE amount of time to simulate that time period. I wonder if there is a way to speed up the simulation...
 

Can you quantify this shocking HUGE amount of time?

http://www.xilinx.com/products/design_tools/logic_design/verification/ise_simulator_faq.htm

isim faq said:
Q. What is ISE Simulator Lite?
A. ISE Simulator Lite is a limited version of the ISE Simulator. There is only one limitation. When the user design + testbench exceeds 50,000 lines of HDL code, the simulator will start to derate the performance of the simulator for that invocation.

You could check if the eval version of modelsim has different limitations such that it doesn't effect this particular simulation. I doubt it, but you could flush 15 minutes into that...

Anyways, just change your workflow so you don't need to run this particular simulation so often...

Mmmh, or another method I just thought of and never used. Simulate it once for lets say 500 us. Then everything is nice and initialized, after which the Real Work [tm] can begin. If you could save that simulation state, and use it as the initial state for all your next sims then that'd help too. That way you could still do meaningful sims without having to spend a lot of time each run just to get through the init phase.

Update: see for example this here link.

$save and $restart should do the trick...
 
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Woah! In that case I'd definitely try $save / $restart.
 

Alright, I just did a behavioral simulation of tb_ddr2_interface and c3_calib_done goes from 0 to 1 at 454.5738 us. At that same time DDR2DQ[15:0] goes from Z to actual data.

...
[/code]

just to know.. how much time does it take to simulate 454.5738 us on your system? What version of ISim are you using (free or not)?
 

The WEBpack version of ISim is crippled (with sleep statements, I guess) and is shockingly slow. With the licensed version, I think it only took 60 seconds or less.

I believe that there are some simulation parameters in the MIG core that reduce the calibration/initialisation time to more manageable levels. Have a look through the documentation. I know I've seen them, but remember fiddling with them and nothing much happening but I wasn't too bothered and didn't investigate any further.
 

Did it work now to simulate the calibration?
Usually Io-Models & physics will have to be added to the functional models in order to simulate these physical dirt effects and make the simulation run.
 

Hello fpgaengineer,
I stopped working on the simulation as I started struggling with the "real" hardware ( I'm still trying to find out what is really happening in the above-mentioned example, although I don't have much time now to dedicate to Atlys; and lately my dedication to the project has slowed down a little), but thank you for your suggestion, I will investigate more on that..
 

I'm completely stuck in this problem. Every attempt I try to drive the DDR2 RAM module seems to fail....
I don't know where to hit my head now... :-?
does anyone know of a working example with DDR2 ?
 

I "solved" the problem using a soft core processor, I have other problems now (unable to stream HDMI pictures at a decent speed because of busted USB port and my only alternatives are either the SLOW UART or Ethernet which I'm unable to operate :sad:.... I know life is painful... ) will put the details on another thread as I'm going OT now...


Elektronman
 

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