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Recent content by elektor

  1. E

    Who has the SoC encounter Lab?

    soc encounter workshop pdf Maybe you have this io lef (CIC vesion) Can you share with us ?
  2. E

    I need umc18io3v5v_6lm_cic.lef ... please

    cbdk018_umc_artisan Hi, I need CBDK018_UMC_Artisan/CIC/SE/umc18io3v5v_6lm_cic.lef Only one file is needed for me... Maybe someone could share with me ?
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    What is common use file format for I/O pads in ASIC flow ?

    Re: What is common use file format for I/O pads in ASIC flow Of course I've understood that it is very different. But for example Silicon Ensemble had *.ioc file with IO Pads location. Regarding of other PAD issues... Have you got any materials about these rules. For example: how many...
  4. E

    What is common use file format for I/O pads in ASIC flow ?

    asic i/o pads Hi, I think about something similar like for example UCF in FPGA xilinx. Mainly I'm focus on forward-backward annotation with information about IO Pads placement in ASIC flow. Maybe someone has some materials or information about this topic ? What format has SOC Encounter for...
  5. E

    Replacement for +incdir when using vcom

    I think that vcom desn't have replacement for +incdor because this option is for particular feature in verilog. It points at dirs with included files. In VHDL (vcom) generic file is compiled similar like the rest core files. Regards Elektor
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    Help: C@dence Ic cannot start after installation of LDV50

    Re: Help: C@dence Ic cannot start after installation of LDV5 Hi, You must check enviroment variables : CDS_INST_DIR, LD_LIBRARY_PATH and PATH Regards Elektor
  7. E

    AMBA Bus Verification tools

    Hi, My boss gave me an issue to get information about AMBA Bus Verifiaction tools subject. So I have a few question: 1. Does anybody use this kind of tools ? I mean for example : ACT by Synoposys or SolidPC by Saros. (I would like to test AHB and AXI bus version) 2. Maybe anybody knows the...
  8. E

    Anyone used "OCP" to design SoC?

    Hi, I have a question about OCP. Could you explain me difference between interface and socket?? They clearly wrote that it is not the same .... Regards Elektor
  9. E

    how to design a chip to encode VGA signal to TV signal?

    Hi, I designed similar design. We used ADV 7179 from Analog Devices Very nice chip, but requires I2C for configuration. Regards Elektor
  10. E

    How to make .do-like macro files in NC-VHDL simulator?

    Re: NCLaunch help Hi, In GUI you can enter command : input /your path/compile.do Regards Elektor
  11. E

    Scan insertion script with SMIC or TSMC standard libraries

    Re: About Scan insertion Hi, Scripts for scan synthesis can be very different in particular designs. Could you provide more details where you have problems ? Maybe then I'll can help you. Regards Elektor
  12. E

    Are there any free power estimators ?

    Re: power estimators Hi, I don'n think so that you find any good free soft for power estimation. I use PrimePower by Synopsys . It's good but not free Regards Elektor
  13. E

    Capturing Switching Activity Synopsys-Modelsim

    modelsim vcd add reference Hi suituse, Ad1. I use "vcd add" instruction. I know that "vcd add" generated vcd file in VCD format and "vcd dumpports" vcd file in EVCD format, but I dont think that Prime Power can use additional information from EVCD. Big importance have good parasitic...
  14. E

    Which tools are needed for ASIC development flow?

    Re: ASIC Development Tools I don't think so. There is no evaluation version any above s/w. Elektor
  15. E

    Which tools are needed for ASIC development flow?

    Re: ASIC Development Tools Hi, This soft are very, very valuable. Synopsys, Cadence and others companies has different prices depending on how your company can negotiate ;) and how many licenses you want. For example : DC can cost ca 150k $, SOC Encounter much more. Regards Elektor

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