Which tools are needed for ASIC development flow?

[Renjith]

ASIC Development Tools

Hi all,
i wanted to know, which r the tools reqd for an ASIC developement flow.
i'm an FPGA designer, and i'm working on Xilinx ISE, which covers the whole design flow task(from design entry to implementation).
Since i'm new to ASIC development, i don't have a clear picture of the best tools related to ASIC ->synthesis, Floorplan, P&R, Timing Analysis etc....

Thnx in advance....
Renv

 

[elektor]

Re: ASIC Development Tools

Hi

In ASIC Design Flow :
among others...
1. Synthesis : Synopsys Design Compiler
2. Floorplan and P&R ( include clocks) : Cadence SOC Encounter
3. Functional Verification : Synopsys Formality
4. Power Analysis : Synopsys Prime Power
5. Timing Analysis : Synopsys Prime Time or Design Compiler


Regards :

Elektor

 

[Renjith]

ASIC Development Tools

Hi Elektor
Thnx for a fast reply....
Do u have an idea abt the pricing issues of these tools

 

[elektor]

Re: ASIC Development Tools

Hi,

This soft are very, very valuable.
Synopsys, Cadence and others companies has different prices depending on how your company can negotiate and how many licenses you want.

For example : DC can cost ca 150k $, SOC Encounter much more.

Regards
Elektor

 

[Renjith]

ASIC Development Tools

hi elektor,
Whether Evaluation versions of these s/w r available?

 

[elektor]

Re: ASIC Development Tools

I don't think so.
There is no evaluation version any above s/w.

Elektor