Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Currently I use power compiler to do post layout power esimation of my block.
ie use the SOCE netlist and do post layout simulation to generate vcd/saif.
annotate the vcd/saif to power compiler along with the netlist, sdf to report power.
is there any more accurate method apart from doing...
Anyone got this warning with change_names command? Safe to ignore?
change_names -rule verilog -hierarchy
Warning: The specified replacement character (_) is conflicting with the specified allowed or restricted character. (UCN-4)
1
Hi folks,
After reporting post layout power in power compiler, I noticed that out of the 2 blocks I have 1 block (SPI) consumes 35% -power and another block(ECG_CQH) consumes less than 1% power. The report doesnt show where does the remaining power goes. ANy idea where is remaining power...
I have inserted integrated clock gate cells in my design in DC and during clock tree synthesis, Encounter inserts the CLK buffers before the clock gate. This causes the buffer to run, when there is no clock required. ANyone know how to move the clock buffers after the clock gate cells, so that...
Hi folks,
I get the below warning of partially routed nets in SoC Encounter. However verifyconnectivity check passes with 0 violations/warnings.
Is this something, I should be concerned about?:???:
#WARNING (NRDB-1005) Can not establish connection to PIN Q at (371.700 113.775) on MET1 for...
Using SoCE after sometime. have an issue.
I have a verilog netlist in which an SRAM module is instantiated.
The power supply name of SRAM in the netlist & in SRAM LEF is ramvdd, ramgnd.
For the standard cells, the power supply in LEF file is vdd! & gnd!
Now while routing I need to connect...
ams 0.35
Hi folks,
am designing a digital chip in AMS .35u library. Inorder to reduce power I would like to used a scaled Vdd of 1.2 V instead of the 3.3V (nominal) specified by the vendor.
The has been simulated correctly in Nanosim with the scaled Vdd. However I am unsure whether DRC (esp...
dude,
I think u have to start with the assumption that the minimum size inverter in that process can drive a fanout of load of 1. then just upsize W/L of both PMOS and NMOS by 4 for driving fanout load of 4.
if u need exact numbers, other details like exact value of the fanout load(i.e how...
wireless specific companies are very less.. many companies are doing projects in wireless though...
to name a few
TI
Intel
sasken
beceem commn--> wireless specific.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
