Clock Tree Synthesis with Clock gating.

[eda_wiz]

I have inserted integrated clock gate cells in my design in DC and during clock tree synthesis, Encounter inserts the CLK buffers before the clock gate. This causes the buffer to run, when there is no clock required. ANyone know how to move the clock buffers after the clock gate cells, so that they switch only when the circuit needs clock and save power. I am using SoC Encounter.