eda_wiz
Advanced Member level 2
Using SoCE after sometime. have an issue.
I have a verilog netlist in which an SRAM module is instantiated.
The power supply name of SRAM in the netlist & in SRAM LEF is ramvdd, ramgnd.
For the standard cells, the power supply in LEF file is vdd! & gnd!
Now while routing I need to connect for vdd! and ramvdd to a single PIN/NET . Also gnd! and ramgnd! to a single net.
For this I use following commands.
globalNetConnect vdd! -type pgpin -pin vdd! -inst * -all -verbose
globalNetConnect gnd! -type pgpin -pin gnd! -inst * -all -verbose
#ramvdd and ramgnd are the SRAM supply
globalNetConnect vdd! -type pgpin -pin ramvdd -inst * -all -verbose
globalNetConnect gnd! -type pgpin -pin ramgnd -inst * -all -verbose
globalNetConnect vdd! -type net -net ramvdd -all -verbose
globalNetConnect gnd! -type net -net ramgnd -all -verbose
globalNetConnect gnd! -type tielo -inst * -all -verbose
globalNetConnect vdd! -type tiehi -inst * -all -verbose
I added a power ring for SRAM with following command
selectInst CCU_TOP/DPRAM2048X16
addRing -spacing_bottom 12 -width_left 40 -width_bottom 40 -width_top 40 -spacing_top 12 -layer_bottom MET3 -stacked_via_top_layer MET4 -width_right 40 -around selected -jog_distance 0.7 -offset_bottom 5 -layer_top MET3 -threshold 0.7 -offset_left 5 -spacing_right 12 -spacing_left 12 -type block_rings -offset_right 5 -offset_top 5 -layer_right MET4 -nets {ramvdd ramgnd} -stacked_via_bottom_layer MET1 -layer_left MET4
and another power ring for the enitire block with the command.
addRing -spacing_bottom 5.0 -spacing_top 5.0 -spacing_left 5.0 -spacing_right 5.0 \
-width_bottom 20 -width_top 20 -width_left 20 -width_right 20 \
-layer_bottom MET3 -layer_top MET3 -layer_left MET4 -layer_right MET4 \
-offset_bottom 0.7 -offset_top 0.7 -offset_left 0.7 -offset_right 0.7 \
-stacked_via_bottom_layer MET1 -stacked_via_top_layer MET4 \
-center 1 \
-around core \
-jog_distance 0.7 \
-threshold 0.7 \
-nets { vdd! gnd!}
After doing special route, my ramvdd & vdd! are not routed to a single net.
sroute -connect { blockPin padPin padRing corePin floatingStripe } -layerChangeRange { 1 4 } -blockPinTarget { nearestRingStripe nearestTarget } -padPinPortConnect { allPort oneGeom } -checkAlignedSecondaryPin 1 -blockPin all -allowJogging 1 -crossoverViaBottomLayer 1 -allowLayerChange 1 -targetViaTopLayer 4 -crossoverViaTopLayer 4 -targetViaBottomLayer 1 -nets {ramvdd vdd! ramgnd gnd!}
I want all the pins of ramvdd & ramgnd to be connected to vdd! and gnd!
Any help?
I have a verilog netlist in which an SRAM module is instantiated.
The power supply name of SRAM in the netlist & in SRAM LEF is ramvdd, ramgnd.
For the standard cells, the power supply in LEF file is vdd! & gnd!
Now while routing I need to connect for vdd! and ramvdd to a single PIN/NET . Also gnd! and ramgnd! to a single net.
For this I use following commands.
globalNetConnect vdd! -type pgpin -pin vdd! -inst * -all -verbose
globalNetConnect gnd! -type pgpin -pin gnd! -inst * -all -verbose
#ramvdd and ramgnd are the SRAM supply
globalNetConnect vdd! -type pgpin -pin ramvdd -inst * -all -verbose
globalNetConnect gnd! -type pgpin -pin ramgnd -inst * -all -verbose
globalNetConnect vdd! -type net -net ramvdd -all -verbose
globalNetConnect gnd! -type net -net ramgnd -all -verbose
globalNetConnect gnd! -type tielo -inst * -all -verbose
globalNetConnect vdd! -type tiehi -inst * -all -verbose
I added a power ring for SRAM with following command
selectInst CCU_TOP/DPRAM2048X16
addRing -spacing_bottom 12 -width_left 40 -width_bottom 40 -width_top 40 -spacing_top 12 -layer_bottom MET3 -stacked_via_top_layer MET4 -width_right 40 -around selected -jog_distance 0.7 -offset_bottom 5 -layer_top MET3 -threshold 0.7 -offset_left 5 -spacing_right 12 -spacing_left 12 -type block_rings -offset_right 5 -offset_top 5 -layer_right MET4 -nets {ramvdd ramgnd} -stacked_via_bottom_layer MET1 -layer_left MET4
and another power ring for the enitire block with the command.
addRing -spacing_bottom 5.0 -spacing_top 5.0 -spacing_left 5.0 -spacing_right 5.0 \
-width_bottom 20 -width_top 20 -width_left 20 -width_right 20 \
-layer_bottom MET3 -layer_top MET3 -layer_left MET4 -layer_right MET4 \
-offset_bottom 0.7 -offset_top 0.7 -offset_left 0.7 -offset_right 0.7 \
-stacked_via_bottom_layer MET1 -stacked_via_top_layer MET4 \
-center 1 \
-around core \
-jog_distance 0.7 \
-threshold 0.7 \
-nets { vdd! gnd!}
After doing special route, my ramvdd & vdd! are not routed to a single net.
sroute -connect { blockPin padPin padRing corePin floatingStripe } -layerChangeRange { 1 4 } -blockPinTarget { nearestRingStripe nearestTarget } -padPinPortConnect { allPort oneGeom } -checkAlignedSecondaryPin 1 -blockPin all -allowJogging 1 -crossoverViaBottomLayer 1 -allowLayerChange 1 -targetViaTopLayer 4 -crossoverViaTopLayer 4 -targetViaBottomLayer 1 -nets {ramvdd vdd! ramgnd gnd!}
I want all the pins of ramvdd & ramgnd to be connected to vdd! and gnd!
Any help?