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First, importing std_logic_1164 has solved the problem.
Second, you are right. I was changing, by mistake, the input numbers to unsigned.
It should be as follows:
c <= ('a(3)'&a) + ('b(3)'&b);--to make sign extension.
I have a question:
What I'm doing is because VHDL imposes that the LHS to...
Hello,
What's wrong with this code:
library ieee;
use ieee.numeric_std.all;
entity adder is
port(a,b: in signed(3 downto 0);
c: out signed(4 downto 0));
end entity adder;
architecture adder1 of adder is
begin
c <= ('0'&a) + ('0'&b);
end architecture adder1;
Error given by...
In a packet based comm system using GFSK as a modulation scheme, I want to check for the alternating preamble every 2 bits (0,1 or 1,0), so that if not found drop these 2 bits and check in the next 2
This check isn't done in the base band, but at the IF stage. I need to do it over the IF...
Hello all,
I've a GFSK modem. Packets begin with a preamble of alternating zeros and ones.
The first stage is Frequency offset estimation(FOE) that counts the no of zero crossings(ZC's) within a certain window (16 bits for example)then estimates the carrier freq offset.
I've added a code...
Hello all,
I've correctly synthesized blocks. Then I'm using structural description to build the complete component.
I'm sure the connections are correct and that there're no floating i/p ports, but I get the following error during synthesis:
Xst:1706 - Unit <comp5>: port <x_real<4><7>> of...
Hello
Usually when I want to something to syntesized as a memory, I declare it as a constant. For example as
type my_array3 is array (0 to 4) of sfixed(7 downto -8) ;
constant main_angles: my_array3...
I've this code which introduces an error:
--Signals declarations are as follows:
signal real_int,imag_int:mat3x8;
signal i:int_1;
signal j:ufixed (9 downto 0);
--data types are defined as follows:
type my_array5 is array (0 to 7) of sfixed(7 downto -8) ;
type mat3x8 is array...
Hello
I'm making a VHDL code for fft algorithm
You know that the i/p vector (say 8 samples each is represented in 16 bits) shoud be 1st bit-reverse ordered such as
element 0--->000-------------->000 ,element 0
element 1--->001-------------->100 ,element 4
element 2--->010-------------->010...
1-Make a new project
2-Choose the library tab not source tab
3-Right click, choose "new source"
4-From the list to the left choose "VHDL library"
5-In the file name type "ieee_proposed". In the directory choose your project directory and create a new folder in it with the same name...
Thank you for your reply
But I need to know something, Should I add the package source code as an ordinary source in my project.
I mean add---->add to project--->new source, check-syntax for it then using it in my code as you said.
This's because when I had done this. an error appeard that says...
Hello
I'm using Xlinix10.1 for synthesis, but I have no idea about how to declare a new library in a source file (such as ieee_proposed) and then copy paste the package code to check-syntax it and use it later in my design
Please I need the detailed steps as I've made alot of trials but still...
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