Help with fixed_pkg package in VHDL

[darshkamal]

Hello
I'm using Xlinix10.1 for synthesis, but I have no idea about how to declare a new library in a source file (such as ieee_proposed) and then copy paste the package code to check-syntax it and use it later in my design

Please I need the detailed steps as I've made alot of trials but still have a problem.
Thank you in advance

Hint
The package works very well in Modelsim-SE, but I've found it in ieee library

 

[TrickyDicky]

ISE 10.1 is pretty old. Any chance you can use a newer one (the newest being 13.2)

First of all, you need to include the fixed_pkg source code in your project.

Then in the VHDL code, you declare:

library ieee_proposed;
use ieee_proposed.fixed_pkg.all;

Then you can use the package to your hearts content.

---------- Post added at 11:13 ---------- Previous post was at 11:12 ----------

In modelsim, it is probably called floatfixlib;

you may need to download the source from here: **broken link removed**
and modify it replacing ieee_proposed with floatfixlib.

 

[darshkamal]

Thank you for your reply
But I need to know something, Should I add the package source code as an ordinary source in my project.
I mean add---->add to project--->new source, check-syntax for it then using it in my code as you said.

This's because when I had done this. an error appeard that says "library ieee_proposed is unknown" and I found after some search that I should compile it in a library called ieee_proposed.

All what I need to know is how to add the source file to my project in a proper way so that I can use the package in my design.

 

[Kepsz]

In current ISE, only the sources of the proposed packages present (older version of the linked files from David Bishop), which cannot be used in code. The complete support of VHDL2008 is (according to xilinx's forum) in their roadmap since 2008, but fixed and floating point packages still not supported. U have to use vhdl_93 version of this packages, but that packages are not specialy written for ISE, and gaves a lot of syntax errors.

Theareticaly, u need to do this steps for vhdl_93 version of fixed_pkg:

Download the packages from David Bishop, he is the maintainer of thes packages: **broken link removed**

U need to create new vhdl library (named IEEE_PROPOSED) in librarys tab, not in the new source menu. Add the downloaded files to the library. Then u can use

library ieee_proposed;
use ieee_proposed.fixed_pkg.all;

in your code, but you will see a lot of syntax error realted to fixed_pkg when trying to compile your code. Some of them can be solved by following the package's xilinx specific documentation: **broken link removed**, but not all of them.


I stucked in this part, actualy no one can sad how to fix this problem.
I'm also in Xilinx forums with this problem: http://forums.xilinx.com/t5/Synthesis/compilation-of-ieee-proposed-library-fails-ISE-13-2/td-p/200101/page/2

If u figure it out how to use fixed_pkg, please let me know.

 

[darshkamal]

1-Make a new project
2-Choose the library tab not source tab
3-Right click, choose "new source"
4-From the list to the left choose "VHDL library"
5-In the file name type "ieee_proposed". In the directory choose your project directory and create a new folder in it with the same name ""ieee_proposed"
Click ok,finish ...etc. A message may appear that this directory doesn't exist and asks you if you want to create it.... click ok
6-From this link--->(**broken link removed**) download the zip file named ""source code" for xlinix 11.1
It's located at the middle of the page.Unzip the file.
7-Back again to ISE window
From the library tap right click on the created library "ieee_proposed" and choose "Add source or Add copy of source (I prefer the 2nd choice)"
8-Browse for the file "fixed_float_types_c.vhdl" and open it
Then fixed_pkg_c.vhdl" and "float_pkg_c.vhdl" respectively
9-After adding these files, return back to "Source" tab .You should find the added package files
Check syntax all these files one after the other, there will be no errors isA
10-Now ya can add any new source file of your own codes and compile them by "check syntax"
11-To use the package type these 2 lines:
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;

This what I tried and I think it works .I have some synthesis error, but I think the error is in my code

---------- Post added at 01:13 ---------- Previous post was at 01:05 ----------

This's a counter that runs from 0 to 9 then resets:

---

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use work.my_package_cordic.all;
 
entity counter is
  port(reset_low,clk:in std_logic;
  count:out int_1 :=0);
end entity counter;
------------------------------------
--                                --
------------------------------------
Architecture counter1 of counter is begin
p:process(clk,reset_low) is
variable temp:int_1;
begin
  if reset_low='0' then --active low reset
    temp:=0;
    count<=0;
  end if;
  if clk='1' and clk'event then
    if temp=10 then
      temp:=0;
    end if;
    temp:=temp+1;
    count<=temp-1;
  end if;
end process p;
end Architecture counter1;

---

the tybe int_1 is defined as folllows----->subtype int_1 is integer range 0 to 15;

I receive this error --->"line 13: Signal count cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release."

I'm using Xilinix 10.1.
Any help please ?

 

[TrickyDicky]

remove the end if; after the register, make the clock part an elsif:

process(clk, reset)
begin
  if reset = '1' then
    --async reset
  elsif rising_edge(clk) then
    --sync part
  end if;
end process;

 

[darshkamal]

Thank you. It worked

 

[Kepsz]

Where do u use the fixed_pkg in your code?

 

[K-J]

Where do u use the fixed_pkg in your code?

You used fixed_pkg in places where you want to perform fixed point arithmetic functions.

Kevin Jennings

 

[Kepsz]

I know how it shoud be works, but even if u use the xilinx specific fixed_pkg from David Bishop, you will find 3 errors in the package like this line:

constant NAUF : UNRESOLVED_ufixed (0 downto 1) := (others => '0');

BTW, using the version 1.21 of fixed_pkg insted of version 1.3 was the solution for me. After changing 0 dowto 1 --> 1 downto 0, i can run the synthesis, withouth any problems.

 

[TrickyDicky]

There are no errors with that line. The error is with the Xilinx compiler if it says there is a problem (Quartus has no problem with it). It is deliberatly 0 downto 1, to give an array of length 0 (if you read the comments, it is a null array). Numeric_std defines the same arrays.

 

[Kepsz]

(0 downto 1) works only in ISE if i use the "-use_new_parser yes" option in XST command line. In this case, it just gave warnings:

... fixed_pkg_c.vhdl" Line 1470: Range is empty (null range)