mod operation in VHDL

[cowslip]

vhdl mod

Hi,
what can I do if i want to have xmody in VHDL, where y is not a power of 2? Lets say it is y=48 for example. Then what hardware should I use? I just want to process the remainder.

Thanks in advance!

 

[the_penetrator]

vhdl mod operator

hi there

generally div, mod and exponentation operators are not directly synthesizable. You will probably have to devise an integer-by-integer hardware divider producing what you want (the remainder as you referred to, as well as the quotient result).

In microprocessors, div and mod are usually emulated in software. If needed in hardware the generic integer divider is a *heavy* piece of (hardware).

BTW i can't think right now of a circuit dedicated to solely mod calculation.

 

[EDALIST]

mod vhdl

you use a multiplier.

one way to do it ...

you multimly the y yx1..yx2, y x 3 ,... yxN.
each time compere with x if it is yxN=X , reminder is 0.
if yxN >x then the reminders is x -y x (N-1), else increase N ...

 

[vomit]

vhdl modulus

It depends if y (not power of 2) is variable or constant.

Suppose it is constant, then you can optimize a lot.

You can precalculate a look-up table and leave optimisation to the synthesis tool. It may find a simple function or resort to a distributed RAM to generate the result. If the input range is not excessive (e.g. 8-bit) this may be cheap in terms of FPGA resources.

subtype t_input is natural range 0 to ...;
subtype t_output is natural range 0 to 47;
type t_mod48 is array(t_input) of t_output;

function initialisation_function return t_mod48 is
variable v_result: t_mod48;
begin
... a loop to fill the v_result, using the normal VHDL mod operator.
... as mod is used on constants here, it is synthesizable.
return v_result;
end;

constant mod48 : t_mod48 := initialisation_function;


and then you can simply

output <= mod48(input);

and have the synthesis tool worry about it.

 

[tkbits]

modulo vhdl

For dividing by constants, what do you want the remainder of?

A counter? Use a second counter that counts from 0 to n-1. After reset and before counter overflow, the second counter will always have the remainder of divide-by-n.

Part of an encryption algorithm? Take advantage of modulo arithmetic and use only remainders. (a+b)mod n = (a mod n + b mod n)mod n. And since multiplication is repeated addition, ab mod n = (a mod n)(b mod n)mod n.

 

[cowslip]

mod in vhdl

Thanks to all. Finally I used the standard algorithm for division, with subtractors, because i'd like to implement a xmod y, in one clock cycle.
Vomit's solution seems good but unfortunately x input range is too excessive.
I'm not sure i unsterstand the logic of the second counter solution that tkbis propose. Is it possible to implement that in one clock cycle?

 

[hamed_sotoudi]

if y is constant and you want to get x mod y multiply x by 1/y then remove high bits and multiply fractional section by y that's your remainder.

 

[darshkamal]

Re: mod in vhdl

Thanks to all. Finally I used the standard algorithm for division, with subtractors, because i'd like to implement a xmod y, in one clock cycle.
Vomit's solution seems good but unfortunately x input range is too excessive.
I'm not sure i unsterstand the logic of the second counter solution that tkbis propose. Is it possible to implement that in one clock cycle?

Hello cowslip
What's the standard algorithm for division you have used ?

 

[venky.817]

Re: mod in vhdl

What is that algorithm to calculate x mod y using subtraction operation? i have also same problem...

 

[FvM]

If you are targetting a parallel ("one clock cycle") implementation, writing mod in VHDL or % in Verilog can be expected to give you an optimal solution in terms of resource usage and speed. If speed isn't an issue, you possibly prefer a sequential divider.