Problem with simple 4-bit adder vhdl code

[darshkamal]

Hello,
What's wrong with this code:

library ieee;
use ieee.numeric_std.all;

entity adder is
  port(a,b: in signed(3 downto 0);
       c: out signed(4 downto 0));
end entity adder;

architecture adder1 of adder is
begin
  c <= ('0'&a) + ('0'&b);
end architecture adder1;

Error given by modelsim compiler is:
** Error: C:/Modeltech_pe_edu_10.2a/examples/adder/test.vhd(11): No feasible entries for infix operator "&".
** Error: C:/Modeltech_pe_edu_10.2a/examples/adder/test.vhd(11): No feasible entries for infix operator "&".
** Error: C:/Modeltech_pe_edu_10.2a/examples/adder/test.vhd(11): Bad expression in left operand of infix expression "+".
** Error: C:/Modeltech_pe_edu_10.2a/examples/adder/test.vhd(11): Bad expression in right operand of infix expression "+".
** Error: C:/Modeltech_pe_edu_10.2a/examples/adder/test.vhd(11): Type error resolving infix expression "+" as type ieee.NUMERIC_STD.SIGNED.
** Error: C:/Modeltech_pe_edu_10.2a/examples/adder/test.vhd(12): VHDL Compiler exiting

Thank you in advance

- - - Updated - - -

Does the concatenation operator not work with signed vectors?

 

[FvM]

You need to import std_logic_1164 to make it work.

The concatenation is effectively changing the input numbers to unsigned, it this what you want? For regular signed addition, you'll use resize() instead. It's sufficient to resize one operand, the other will be resized automatically.

 

[darshkamal]

First, importing std_logic_1164 has solved the problem.
Second, you are right. I was changing, by mistake, the input numbers to unsigned.
It should be as follows:

c <= ('a(3)'&a) + ('b(3)'&b);--to make sign extension.

I have a question:
What I'm doing is because VHDL imposes that the LHS to the equal sign of addition is the same size as the RHS' operands.
Will this concatenated bit be removed during synthesis

 

[FvM]

c <= ('a(3)'&a) + ('b(3)'&b);--to make sign extension.

You can also write

c <= resize(a,5) + resize(b,5);

or even shorter

c <= resize(a,5) + b;

What I'm doing is because VHDL imposes that the LHS to the equal sign of addition is the same size as the RHS' operands.
Will this concatenated bit be removed during synthesis

I guess, you don't want the sign extension before addition to be removed. Otherwise could write

c <= resize(a+b,5);

Which restricts the result to 4 bit, possibly causing an overflow, e.g. 5 + 6 = - 5