Defining a constant using for loop (VHDL)

[darshkamal]

Hello
Usually when I want to something to syntesized as a memory, I declare it as a constant. For example as

type my_array3 is array (0 to 4) of sfixed(7 downto -8) ;
constant main_angles: my_array3 :=(to_sfixed(0.0,7,-8),to_sfixed(1.5708,7,-8),to_sfixed(3.1416,7,-8),to_sfixed(4.7124,7,-8),to_sfixed(6.2832,7,-8));

and these 2 lines are located in a package

Now I want to define a constant that will hold 1024 values and I want to use a for loop to facilate the matters and not write 1024 value by hand.
As an example

for i IN 0 to 1023
constant A(i):=i;

I don't know the right syntax or if the for loop can be used inside a process only or not.
Can anyone help please ?

 

[FvM]

Sounds like a job for a generate statement or a function.