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In the attached sub 1V bandgap reference circuit, the voltage across R3b should be a PTAT. In simulation I get a CTAT for both the legs. What could be the possible reasons?
I am trying to design a BGR for which I have designed an op-amp. When I run stb analysis, I find that the loop is unstable. This may be due to the presence of both positive and negative feedback. How can this be rectified?
Dear all,
I am running a cross function after transient analysis to find a certain instant instant of time. I would like to use this time (as calculated by cross func) in trans + ac analysis. How can this be done?
I have built differential input and differential output 2-stage opamp with open loop Low-frequency gain of 60 dB and UGB 600MHz. I have tried to build a closed-loop amplifier of 6DB using feedback resistors. When i do a noise analysis on the op-amp in LT spice, I get a curve as attached. Can...
Dear All,
In a switched capacitor amplifier, it is seen that the SNR degrades as the input frequency increases close to fs/2 where fs is the sampling frequency. Why?
Dear all,
I am trying to simulate .noise in cadence for a flip-around sample and hold circuit. The sampling frequency is 4MHz. I have connected the inputs to common mode. The freq range is from 1 to 2MHz. I see peaking in the noise response at 165KHz. I think I am missing out on something.
Is...
Dear all,
I am trying to simulate .noise in cadence for a flip-around sample and hold circuit. The sampling frequency is 4MHz. I have connected the inputs to common mode. The freq range is from 1 to 2MHz. I see peaking in the noise response at 165KHz. I think I am missing out on something.
Is...
Dear All,
I have a sample and hold circuit built using a high gain opamp. I would like to check what is the noise introduced due to charge injection of the switches and op-amp separately. How can I do that?
Dear all,
I am trying to simulate a 12-bit pipeline ADC in cadence. In the first 4 stages of the ADC are MDAC and comparators designed using PMOS and NMOS. The LSB stages are coded using Verilog A model. Now, I give a sine wave of the input and try to take a fft of it. I wanted to know how...
Why is the NMOS transistor in footed dynamic logic families always present after the combinational logic is realized? Why cannot it be placed just below the PMOS transistor before the combinational logic is realized?
I am attaching the circuit here. I get the required current from both these circuits. The gain and phase margin of the amplifier using these circuits are the same. But when I use this op-amp in the SC sample and hold amplifier the output is distorted. The circuit with one mirror does not work...
I have designed a 2 stage op-amp to be used in a switched capacitor circuit. The first stage of the op-amp is diff input and diff output op-amp with NMOS input pair. The NMOS current source carries a current of 640uA. I am mirroring it from 10uA current source. So, the ratio of (W/l) = 1:64...
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