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Recent content by chifalcon

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    Realization of dual_clock with fixed phase shift in Low Frequency Mode?

    Hello, imbichie, Thanks for your reply. I am a rookie in DCM. So please correct my design. Here, in Xilinx DCM, a phase shift resolution 256 of the CLKIN's clock period can be achieved. in my design, the higher phaseshift resolution the better. If I use a f/2 directly from 6MHz to...
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    Realization of dual_clock with fixed phase shift in Low Frequency Mode?

    Hi, I need to generate a couple of clocks which has fixed and adjustable phaseshift. One frequency is 2 times of the other one. e.g. in my case, one frequency is 3Mhz, one is 6Mhz. I use DCM due to it's merit of high phase shift resolution. Becasue my design work in LFM (low...
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    How to remove the heat sinker on Xilinx FPGA chip?

    Well, I've already done it. I don't know the type of the heatsink. It's deployed on a type II (hat shape) lid. I just used a blade to leverage the heatsink off from a corner of it. It seems not difficulty. The adhesive is soft due to the hot weather here. So, it was removed just easily. Thanks!!
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    How to remove the heat sinker on Xilinx FPGA chip?

    Hi, I need to measure the tiny EM leakage from cells of the FPGA chip. So I have to locate the EM probe to the surface of the chip as close as possible. However, the heatsinker covers the surface of the chip . Can you please give me some guidances to remove the heat sinker on the FPGA ...
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    What's the meaning of the black while eye on each Xilinx Slice?

    Hi, I tried a full combination design on Xilinx FPGA. A balck and while circle appears in every used SLICE. What does this mean? Thanks!
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    Can P&R the post-map simulation model?

    Hi, I need to modify the netlist generated from "Generate Post-map simulation model"(or by netgen). After the netlist modifcation, can I continue the work of place&route based on the modified simulation model netlist? Or this post-map simulation model is just for the simulation? Thanks! Eric
  7. C

    Can P&R the post-map simulation model?

    Hi, I need to modify the netlist generated from "Generate Post-map simulation model"(or by netgen). After the netlist modifcation, can I continue the work of place&route based on the modified simulation model netlist? Or this post-map simulation model is just for the simulation...
  8. C

    Can I disable the use of negative output of D flip-flop in constrainst?

    Hi, rca, I used the "set_dont_use" to exclude most cells except the "and2, or2, inverter and FD1". Because in my project, other cells are not permited. I mean, I must constraint the types of gates, but this constraints are not possible in FPGA synthesizer. So I should first do it in ASIC...
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    Can I disable the use of negative output of D flip-flop in constrainst?

    Hi, I need to transfer my synthesized .v file (a gate-level descripted .v file) from DC to xilinx synthesizer. But the negative output cannot match the hardware resources in Xillinx FPGA. So I have to diable the use of negative output. Can I do that by using some kinds of constriaint scripts...
  10. C

    [SOLVED] How to list all the cells available in my_lib?

    Can I disable the use of negative output of D flip-flop in constrainst? solved................
  11. C

    Constraint the gate types in synthesis?

    Thanks, I could get it now. It's the problem of the linked library.
  12. C

    Constraint the gate types in synthesis?

    Hi, lostinxlation, I tried to use gtech, there are not errors now. But it seems the constrained gates still exist. what is the my_lib I used here? Is it the one shown in "FILE -> Elaborate -> Library"? and Do I need to clean all the constraints previously used before I use the new...
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    Constraint the gate types in synthesis?

    Hi, I am a rookie in ASIC. I was always working in FPGA. But now I need to do a design without certain typles of gates. ( Actually in my design, only "AND2", "OR2" and "Inverter" 3 types of gates are permitted ). In FPGA synthesizer, I cannot constrait the gate types. So, I have to...
  14. C

    How could I get LUT-level netlist in Xilinx ISE?

    Hi, I need to convert the high level design to LUT level netlist, and then make corrections to it. In a paper, author says: "The translate step generates a Verilog netlist that can easily be parsed. This netlist consists out of declarations of primitive modules of the device" The netlist is...
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