Constraint the gate types in synthesis?

[chifalcon]

Hi,
I am a rookie in ASIC. I was always working in FPGA. But now I need to do a design without certain typles of gates. ( Actually in my design, only "AND2", "OR2" and "Inverter" 3 types of gates are permitted ).

In FPGA synthesizer, I cannot constrait the gate types.
So, I have to resort to the ASIC synthesizer to do this work. i. e. Using Design Vision to synthesize my (.v) design by restricting the gate types (only AND2, OR2, Inverter). Then I get a gate-level descripted verilog file. After that, I could continue the following work on FPGA.

I know i need to use attribute "set_dont_use". But I am not sure how to use it.

E.g, should I set the forbidden gates one by one? If it is, what's the maximal number of the gate inputs for a, for example, XOR gate?

set_dont_use {my_lib/XOR2 my_lib/XOR3 my_lib/XOR4 ........}

Can I set to use only the three types of gates? So, the rest gates are all excluded automatically.

Thanks very much in advance!

Eric.

---------- Post added at 19:07 ---------- Previous post was at 18:41 ----------

Sorry for a further question, I checked the libs by typing report_design:

Library(s) Used:

ssc_core (File: /working_tutorial/dv_tutorial/risc_design/libs/core_typ.db)

Local Link Library:

{core_typ.db}

Which libs should I use? "ssc_core" or "core_typ.db"

I tried them both, they all give error:

design_vision> set_dont_use ssc_core/XOR2
Error: Can't find object 'ssc_core/XOR2'. (UID-109)

Can anybody give me some hints?

Thanks!!

Eric

 

[lostinxlation]

If my memory serves, you can use a wildcard (*) if you want.
set_dont_use {my_lib/AND* my_lib/OR* my_lib/XOR* ........}

Or another way is to disable all the cells first, and enable those cells you want to use with remove_attribute command like this(I didn't check the syntax).

set_dont_use {my_lib/* }
remove_attribute {my_lib/INV2} dont_use


Check the man page.

Regarding the error, did you set _dont_use after link ?

 

[phoenixpavan]

Hi Falcon,

Use wild card entry as lostinxlation suggested...but using wildcard entries can sometime lead to performance hit...So do prefer the second option and remove for the cells you need.

cheers,

 

[chifalcon]

Hi, lostinxlation,

I tried to use gtech, there are not errors now.

But it seems the constrained gates still exist.

what is the my_lib I used here? Is it the one shown in "FILE -> Elaborate -> Library"?
and
Do I need to clean all the constraints previously used before I use the new constraints?

Thanks!!

Eric

 

[chifalcon]

Thanks, I could get it now. It's the problem of the linked library.