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What's the meaning of the black while eye on each Xilinx Slice?

Thread starter chifalcon
Start date Jun 29, 2011

Status: Not open for further replies.

Jun 29, 2011

#1

C

chifalcon

Newbie level 6

Hi,
I tried a full combination design on Xilinx FPGA. A balck and while circle appears in every used SLICE. What does this mean?

Thanks!

未命名.jpg

Status: Not open for further replies.

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