Can I disable the use of negative output of D flip-flop in constrainst?

[chifalcon]

Hi,
I need to transfer my synthesized .v file (a gate-level descripted .v file) from DC to xilinx synthesizer. But the negative output cannot match the hardware resources in Xillinx FPGA. So I have to diable the use of negative output. Can I do that by using some kinds of constriaint scripts?

Thanks!!

Eric

 

[rca]

1-you could avoid the usage of certain std cell, with "set_dont_use [get_lib_cells <cell_name>]"
2-could you used a fpga synthesizer like Precision or...
3-Xilinx are able to read the RTL code, no?

 

[chifalcon]

Hi, rca,
I used the "set_dont_use" to exclude most cells except the "and2, or2, inverter and FD1". Because in my project, other cells are not permited. I mean, I must constraint the types of gates, but this constraints are not possible in FPGA synthesizer. So I should first do it in ASIC synthesizer to get the gate-level descripted .v file (which is comprised of the above mentioned 4 types of cells) than then transfer it to FPGA for the following work.

That's why I do it in ASIC tool and then jump to FPGA tools.

The problem now is the one I asked in the thread. In xilinx FPGA, ff has no negative ouput. So I must disable the usage of the negative output of FD1 in DC synthesis in order to match the hardwares in FPGAs.

 

[rca]

Sorry, I'm misunderstanding one point, why you could not used the Xilinx compiler, because this one could read RTL code, and directly targeted the right FPGA? And you could reused your SDC constraint file?

 

[lostinxlation]

Break the timing arc from CK to Qbar or disable it, and see what will happen.