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sram standby mode
Hi to all! I'm new in HSPICE. Can anyone help me make an hspice file of a 6T SRAM in standby mode?.. Your help is greatly appreciated. Thanks.
Here are important questions that would be needed in making the hspice file:
1. What will I use to set the wordline WL to logic '0'...
Hi to all!
I'm currently studying on bus architecture. Can anyone give me a good source and schematic on a Simple Bus architecture? or Can someone explain to me the functions of a Simple bus architecture?.. Thanks!
Hello all! Does anyone know how to plot the gain of a CMOS inverter? How can we get the gain of a CMOS inverter? And how can we plot it in winspice?... Please help me.
Hi all I have a question here about synchronizer. Say, a company wants to sell you a perfect synchronizer.They claim that it never produces a metastable output. The synchronizer consists of a regular latch followed by a high gain comparator that produces a high output for inputs above Vdd/4 and...
invalid entry crc matlab
Hello! Anyone encountered an Invalid entry CRC error during matlab intsallation? If yes, how did you troubleshoot this problem?
Hi all! I just want to ask what are the testability issues in a sequential circuit? Say you are given a sequential circuit, what testability issues you can discuss on that sequential circuit?
I'm not doing a simulation. I'm doing a manual design for this. I'm confused on the count from 0-8 or 1-9... Since there are only 8 states (2^3bits = 8). So we could only have a count from 0-7 or 1-8.What can I do to get 8?..I'm really confused about this...
hi all! Can anyone help me analyze this problem? I'm confused with this.
Design a 3 bit counterlike circuit controlled by the input w. If w=1 then the counter adds 2 to its contents, wrapping around if the count reaches 8 or 9. Thus if the present state is 8 or 9, then the next state becomes 0...
I am dealing with non 6T SRAM in my project because I want to compare the leakage of non 6T SRAM to the conventional 6T SRAM. That is the objective of my project.
Hi all,
Im doing a project about non 6T SRAMs, particularly 7T and 8T SRAMs. I want to compare them by measuring the leakage currents (gate tunneling current and subthreshold current). I also want to compare them to the conventional 6T SRAM. Can anyone tell me how will I get these leakage...
Hello to all!
Can anyone give me a block diagram of a synchronous mixed signal chip? I don't know how it looks. All i know that it has an ADC(Analog-to-Digital Converter), digital baseband processor, ADC output registers, combinational logic and receiving flip-flops. Your help greatly appreciated.
Timing Problem
This is a problem in a homework from Berkeley. I'm looking for a schematic for the synchronous mixed signal chip but I haven't found it yet.
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