synchronizer Question

[cfreng2]

Hi all I have a question here about synchronizer. Say, a company wants to sell you a perfect synchronizer.They claim that it never produces a metastable output. The synchronizer consists of a regular latch followed by a high gain comparator that produces a high output for inputs above Vdd/4 and a low output for inputs below the point. They argue that even if the flip flop enters metastability, its output will hover vdd/2 so the synchronizer produces a good high output after the comparator. Tell me why I would'nt buy this synchronizer?

 

[phasePI]

It depends on the specific input signal and speed requirements. There is always a natural probability to metastable. That depends also on the process technology of the semiconductor device.

Most times there is a simple D-FF to sync. In IC you find often two D-FF in series. Sometimes this is expanded up to 4 in series! I don't think you find a circuit with more stages.
With every stage the probability is MUCH more reduced finally going into metastable state.
Then there is the other side how long the device will need to recover. This is also semiconductor process technology specific.

Don't worrry. Just try to make a synchronized system with high-speed signals preferred to be in sync. Slower ones being more asynch.

That's why a microprocessor is ALWAYS clock synched to it own clock source.


regards -
Henry

 

[cfreng2]

How can you defend that the synchronizer described on the first post to be unreal? Can you tell me if the given specification is realizable?