cfreng2
Junior Member level 3
Hi all,
Can anyone help me solve this problem? or at least give me anything to read that could help me answer this problem.
Here it is:
A synchronous mixed-signal chip designed to work at 750 MHz has the same clock
source, but independent clock trees for the A/D converter (ADC) and digital baseband signal processor. Both clock tree insertion delays are dependent on operating conditions. ADC clock insertion delay is 1.2ns±0.1ns, and the digital clock tree insertion delay is 1.5ns±0.1ns. Additionally, the local skew of both clocks is ±70ps. The ADC output register and the receiving flip-flop on the digital side are edge-triggered and have setup times of 70ps, clock-to-output delays of 150ps and 100ps hold times.
Derive the minimum and maximum logic delays for the block of combinational logic
between the ADC registers and flip-flops on the digital side.
Can anyone help me solve this problem? or at least give me anything to read that could help me answer this problem.
Here it is:
A synchronous mixed-signal chip designed to work at 750 MHz has the same clock
source, but independent clock trees for the A/D converter (ADC) and digital baseband signal processor. Both clock tree insertion delays are dependent on operating conditions. ADC clock insertion delay is 1.2ns±0.1ns, and the digital clock tree insertion delay is 1.5ns±0.1ns. Additionally, the local skew of both clocks is ±70ps. The ADC output register and the receiving flip-flop on the digital side are edge-triggered and have setup times of 70ps, clock-to-output delays of 150ps and 100ps hold times.
Derive the minimum and maximum logic delays for the block of combinational logic
between the ADC registers and flip-flops on the digital side.