non 6T SRAM project help

[cfreng2]

Hi all,

Im doing a project about non 6T SRAMs, particularly 7T and 8T SRAMs. I want to compare them by measuring the leakage currents (gate tunneling current and subthreshold current). I also want to compare them to the conventional 6T SRAM. Can anyone tell me how will I get these leakage currents? On what operating conditions will I get these leakage currents? I hope someone could help me with this. Your help and ideas is greatly appreciated.

 

[sunjimmy]

May you explain why you use 7T/8T architecture for SRAM design ?
As far as i know, the leakage of 6T SRAM comes from process issue, not circuit issue. Because usually SRAM bit cell layout doesn't follow the layout design rule in order to save area.

 

[cfreng2]

I am dealing with non 6T SRAM in my project because I want to compare the leakage of non 6T SRAM to the conventional 6T SRAM. That is the objective of my project.

 

[sunjimmy]

May you kindly provide the schematic or papers regarding to 7T/8T SRAM bit cell ?

As far as i know, the leakage current comes from;
1. device Ioff current
2. junction leakage
3. gate-oxide leakage in nm design

Hope it helps